CY8C9560A-24AXI Datasheet CY8C9520A-24PVXI, CY8C9560A-24AXI, CY8C9540A-24PVXI | P1-P3

CY8C9520A

CY8C9540A

CY8C9560A

20-, 40-, and 60-Bit I/O Expander

with EEPROM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 38-12036 Rev. *I Revised April 1, 2015

Features

■ I

C interface logic electrically compatible with SMBus

■ Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)

I/O data pins independently configurable as inputs, outputs,

Bi-directional input/outputs, or PWM outputs

■ 4/8/16 PWM sources with 8-bit resolution

■ Extendable soft addressing algorithm allowing flexible I

address configuration

■ Internal 3-/11-/27-Kbyte EEPROM

■ User default storage, I/O port settings in internal EEPROM

■ Optional EEPROM write disable (WD) input

■ Interrupt output indicates input pin level changes and pulse

width modulator (PWM) state changes

■ Internal power on reset (POR)

■ Internal configurable watchdog timer

Top Level Block Diagram

Overview

The CY8C95xxA is a multi-port I/O expander with on board user

available EEPROM and several PWM outputs. All devices in this

family operate identically but differ in I/O pins, number of PWMs,

and internal EEPROM size.

The CY8C95xxA operates as two I

C slave devices. The first

device is a multi port I/O expander (single I

C address to access

all ports through registers). The second device is a serial

EEPROM. Dedicated configuration registers can be used to

disable the EEPROM. The EEPROM uses 2-byte addressing to

support the 28 Kbyte EEPROM address space. The selected

device is defined by the most significant bits of the I

C address

or by specific register addressing.

The I/O expander's data pins can be independently assigned as

inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.

The individual data pins can be configured as open drain or

collector, strong drive (10 mA source, 25 mA sink), resistively

pulled up or down, or high impedance. The factory default

configuration is pulled up internally.

The system master writes to the I/O configuration registers

through the I

C bus. Configuration and output register settings

are storable as user defaults in a dedicated section of the

EEPROM. If user defaults were stored in EEPROM, they are

restored to the ports at power up. While this device can share the

bus with SMBus devices, it can only communicate with I

masters. The I

C slave in this device requires that the I

C master

supports clock stretching.

There is one dedicated pin that is configured as an interrupt

output (INT) and can be connected to the interrupt logic of the

system master. This signal can inform the system master that

there is incoming data on its ports or that the PWM output state

was changed.

The EEPROM is byte readable and supports byte-by-byte

writing. A pin can be configured as an EEPROM Write Disable

(WD) input that blocks write operations when set high. The

configuration registers can also disable EEPROM operations.

The CY8C95xxA has one fixed address pin (A0) and up to six

additional pins (A1-A6), which allow up to 128 devices to share

a common two wire I

C data bus. The Extendable Soft

Addressing algorithm provides the option to choose the number

of pins needed to assign the desired address. Pins not used for

address bits are available as GPIO pins.

There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)

independently configurable 8-bit PWMs. These PWMs are listed

as PWM0-PWM15. Each PWM can be clocked by one of six

available clock sources.

EEPROM

User

Settings

Area

User

Available

Area

Control

Unit

GPort 0

GPort 1

GPort 2

GPort 3

GPort 7

PWM 0

PWM 15

Power-on-Reset

1.5 MHz

93.75 kHz

Divider (1-255)

Clocks

32 kHz

24 MHz

SCL

SDA

8 Bit IO

5 Bit IO

3 Bit IO

or A4-A6

4 Bit IO

or A1-A3, WD6

8 Bit IO

INT

Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround.

CY8C9520A

CY8C9540A

CY8C9560A

Document Number: 38-12036 Rev. *I Page 2 of 32

Contents

Architecture ......................................................................3

Applications .................................................................3

Device Access Addressing ..............................................4

Serial EEPROM Device ...............................................4

Multi Port I/O Device ...................................................4

Pinouts ..............................................................................5

28-Pin Part Pinout .......................................................5

48-Pin Part Pinout .......................................................6

100-Pin Part Pinout .....................................................7

Pin Descriptions ...............................................................9

Extendable Soft Addressing ........................................9

Interrupt Pin (INT) ........................................................9

Write Disable Pin (WD) ...............................................9

External Reset Pin (XRES) .........................................9

Working with PWMs ....................................................9

Input Port Registers (00h–07h) .................................11

Output Port Registers (08h–0Fh) ..............................11

Int. Status Port Registers (10h–17h) .........................12

Port Select Register (18h) .........................................12

Interrupt Mask Port Register (19h) ............................12

Select PWM Register (1Ah) ......................................12

Inversion Register (1Bh) ............................................12

Port Direction Register (1Ch) ....................................12

Drive Mode Registers (1Dh–23h) ..............................12

PWM Select Register (28h) .......................................12

Config (29h) ...............................................................13

Period Register (2Ah) ................................................13

Pulse Width Register (2Bh) .......................................13

Divider Register (2Ch) ...............................................13

Enable Register (2Dh) ...............................................13

Device ID/Status Register (2Eh) ...............................13

Watchdog Register (2Fh) ..........................................14

Command Register (30h) ..........................................14

Commands Description .................................................14

Store Config to E2 POR Defaults Cmd (01h) ............14

Restore Factory Defaults Cmd (02h) .........................14

Write E2 POR Defaults Cmd (03h) ............................14

Read E2 POR Defaults Cmd (04h) ...........................15

Write Device Config Cmd (05h) .................................15

Read Device Config Cmd (06h) ................................15

Reconfigure Device Cmd (07h) .................................15

Electrical Specifications ................................................16

Absolute Maximum Ratings .......................................16

Operating Temperature .............................................16

DC Electrical Characteristics .....................................17

AC Electrical Characteristics .....................................19

Packaging Dimensions ..................................................21

Thermal Impedances ................................................. 23

Solder Reflow Specifications .....................................23

Features and Ordering Information ..............................24

Ordering Code Definitions .........................................24

Acronyms ........................................................................25

Reference Documents ....................................................25

Document Conventions .................................................25

Units of Measure ....................................................... 25

Numeric Conventions ....................................................25

Numeric Naming ........................................................25

Glossary ..........................................................................26

Errata ...............................................................................30

Part Numbers Affected .............................................. 30

Qualification Status ...................................................30

Errata Summary ........................................................30

Document History Page .................................................31

Sales, Solutions, and Legal Information ......................32

Worldwide Sales and Design Support ....................... 32

Products ....................................................................32

PSoC® Solutions ...................................................... 32

Cypress Developer Community .................................32

Technical Support .....................................................32

CY8C9520A

CY8C9540A

CY8C9560A

Document Number: 38-12036 Rev. *I Page 3 of 32

Architecture

The Top Level Block Diagram on page 1 illustrates the device

block diagram. The main blocks include the control unit, PWMs,

EEPROM, and I/O ports. The control unit executes commands

received from the I

C bus and transfers data between other bus

devices and the master device.

The on chip EEPROM can be separated conventionally into two

regions. The first region is designed to store data and is available

for byte wide read/writes through the I

C bus. It is possible to

prevent write operations by setting the WD pin to high. All

EEPROM operations can be blocked by configuration register

settings. The second region allows the user to store the port and

PWM default settings using special commands. These defaults

are automatically reloaded and processed after device power on.

The number of I/O lines and PWM sources are listed in the

following table.

There are four pins on GPort 2 and three on GPort 1 that can be

used as general purpose I/O or EEPROM Write Disable (WD)

and I

C-address input (A1-A6), depending on configuration

settings.

Figure 1 shows the single port logical structure. The Port Drive

Mode register gives the option to select one of seven available

modes for each pin separately: pulled up/down, open drain

high/low, strong drive fast/slow, or high impedance. By default

these configuration registers store values setting I/O pins to be

pulled up. The Invert register enables inversion of the logic of the

Input registers separately for each pin. The Select PWM register

assigns pins as PWM outputs. All of these configuration registers

are read/writable using corresponding commands in the

multi-port device.

Figure 1. Logical Structure of the I/O Port

The Port Input and Output registers are separated. When the

Output register is written, the data is sent to the external pins.

When the Input register is read, the external pin logic levels are

captured and transferred. As a result, the read data can be

different from written Output register data. This enables imple-

mentation of a quasi-bidirectional input-output mode, when the

corresponding binary digit is configured as pulled up/down

output.

Each port has an Interrupt Mask register and an Interrupt Status

there has been a change in the corresponding input line since

the last read of that Interrupt Status register. The Interrupt Status

enables/disables activation of the INT line when input levels are

changed. Each high in the Interrupt Mask register masks

(disables) an interrupt generated from the corresponding input

line.

Applications

Each GPIO pin can be used to monitor and control various board

level devices, including LEDs and system intrusion detection

devices.

The on board EEPROM can be used to store information such

as error codes or board manufacturing data for read-back by

application software for diagnostic purposes.

Table 1. GPIO Availability

Port CY8C9520A CY8C9540A CY8C9560A

GPort 0 8 bit 8 bit 8 bit

GPort 1 5-8 bit

[1]

5-8bit

[1]

5-8 bit

[1]

GPort 2 0-4 bit

[1]

0-4it

[1]

0-4 bit

[1]

GPort 3 – 8 bit 8 bit

GPort 4 – 8 bit 8 bit

GPort 5 – 4 bit 8 bit

GPort 6 – – 8 bit

GPort 7 – – 8 bit

PWMs 4 8 16

GPortx

7 Drive Mode

Registers

Drive Mode

Pull-Up

Drive Mode

Hig h Z

Interrupt

Status

Interrupt

Mask

Pin Direction Inversion

Input Register

Select PWM

Output

8 Bit IO

Data

PWMs

Note

1. This port contains configuration-dependant GPIO lines or A1-A6 and WD lines.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

CY8C9560A-24AXI

Mfr. #:

Buy CY8C9560A-24AXI

Manufacturer:

Cypress Semiconductor

Description:

Interface - I/O Expanders 60BIT IO EXPANDER W/EEPROM

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