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CY8C9560A-24AXI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
CY8C9520A
CY8C9540A
CY8C9560A
Document Number: 38-12036 Rev. *I Page 7 of 32
100-Pin Part Pinout
Table 5. 100-Pin Part Pinout (TQFP)
Pin
No.
Name Description
Pin
No.
Name Description
1 DNU DNU = Do Not Use; leave floating. 51 DNU DNU = Do Not Use; leave floating.
2 DNU DNU = Do Not Use; leave floating. 52 GPort5_Bit1_PWM8 Port 5, Bit 1, PWM 8.
3 GPort0_Bit3_PWM1 Port 0, Bit 3, PWM 1. 53 GPort5_Bit0_PWM10 Port 5, Bit 0, PWM 10.
4 GPort0_Bit4_PWM7 Port 0, Bit 4, PWM 7. 54 GPort5_Bit4_PWM12 Port 5, Bit 4, PWM 12.
5 GPort0_Bit5_PWM5 Port 0, Bit 5, PWM 5. 55 GPort5_Bit5_PWM14 Port 5, Bit 5, PWM 14.
6 GPort0_Bit6_PWM3 Port 0, Bit 6, PWM 3. 56 GPort4_Bit7_PWM8 Port 4, Bit 7, PWM 8.
7 GPort0_Bit7_PWM1 Port 0, Bit 7, PWM 1. 57 GPort4_Bit6_PWM10 Port 4, Bit 6, PWM 10.
8 GPort3_Bit0_PWM7 Port 3, Bit 0, PWM 7. 58 GPort4_Bit5_PWM12 Port 4, Bit 5, PWM 12.
9 GPort3_Bit1_PWM5 Port 3, Bit 1, PWM 5. 59 GPort4_Bit4_PWM14 Port 4, Bit 4, PWM 14.
10 GPort3_Bit2_PWM3 Port 3, Bit 2, PWM 3. 60 DNU DNU = Do Not Use; leave floating.
11 GPort3_Bit3_PWM1 Port 3, Bit 3, PWM 1. 61 DNU DNU = Do Not Use; leave floating.
12 DNU DNU = Do Not Use; leave floating. 62 XRES Active high external reset with internal pull down.
13 DNU DNU = Do Not Use; leave floating. 63 GPort4_Bit3_PWM0 Port 4, Bit 3, PWM 0.
14 DNU DNU = Do Not Use; leave floating. 64 GPort4_Bit2_PWM2 Port 4, Bit 2, PWM 2.
15 V
SS
Ground connection. 65 V
SS
Ground connection.
16 GPort3_Bit4_PWM15 Port 3, Bit 4, PWM 15. 66 GPort4_Bit1_PWM4 Port 4, Bit 1, PWM 4.
17 GPort3_Bit5_PWM13 Port 3, Bit 5, PWM 13. 67 GPort4_Bit0_PWM6 Port 4, Bit 0, PWM 6.
18 GPort3_Bit6_PWM11 Port 3, Bit 6, PWM 11. 68 GPort1_Bit7_PWM0/A4 Port 1, Bit 7, PWM 0, Address 4.
19 GPort3_Bit7_PWM9 Port 3, Bit 7, PWM 9. 69 GPort1_Bit6_PWM2/A5 Port 1, Bit 6, PWM 2, Address 5.
20 GPort5_Bit7_PWM15 Port 5, Bit 7, PWM 15. 70 GPort1_Bit5_PWM4/A6 Port 1, Bit 5, PWM 4, Address 6.
21 GPort5_Bit6_PWM13 Port 5, Bit 6, PWM 13. 71 DNU DNU = Do Not Use; leave floating.
22 GPort5_Bit2_PWM11 Port 5, Bit 2, PWM 11. 72 GPort1_Bit4_PWM6 Port 1, Bit 4, PWM 6.
23 GPort5_Bit3_PWM9 Port 5, Bit 3, PWM 9. 73 DNU DNU = Do Not Use; leave floating.
24 I
2
C Serial Clock (SCL) I
2
C Clock. 74 GPort1_Bit3_PWM0 Port 1, Bit 3, PWM 0.
25 DNU DNU = Do Not Use; leave floating. 75 DNU DNU = Do Not Use; leave floating.
26 DNU DNU = Do Not Use; leave floating. 76 DNU DNU = Do Not Use; leave floating.
27 DNU DNU = Do Not Use; leave floating. 77 GPort1_Bit2_PWM2 Port 1, Bit 2, PWM 2.
28 I
2
C Serial Data (SDA) I
2
C Data. 78 DNU DNU = Do Not Use; leave floating.
29 GPort2_Bit3_PWM11/A1 Port 2, Bit 3, PWM 11, Address 1. 79 GPort1_Bit1_PWM4 Port 1, Bit 1, PWM 4.
30 A0 Address 0. 80 DNU DNU = Do Not Use; leave floating.
31 DNU DNU = Do Not Use; leave floating. 81 GPort1_Bit0_PWM6 Port 1, Bit 0, PWM 6.
32 V
dd
Supply voltage. 82 V
dd
Supply voltage.
33 DNU DNU = Do Not Use; leave floating. 83 V
dd
Supply voltage.
34 V
SS
Ground connection. 84 V
SS
Ground connection.
35 DNU DNU = Do Not Use; leave floating. 85 V
SS
Ground connection.
36 GPort7_Bit7_PWM15 Port 7, Bit 7, PWM 15. 86 GPort6_Bit0_PWM0 Port 6, Bit 0, PWM 0.
37 GPort7_Bit6_PWM14 Port 7, Bit 6, PWM 14. 87 GPort6_Bit1_PWM1 Port 6, Bit 1, PWM 1.
38 GPort7_Bit5_PWM13 Port 7, Bit 5, PWM 13. 88 GPort6_Bit2_PWM2 Port 6, Bit 2, PWM 2.
39 GPort7_Bit4_PWM12 Port 7, Bit 4, PWM 12. 89 GPort6_Bit3_PWM3 Port 6, Bit 3, PWM 3.
40 GPort7_Bit3_PWM11 Port 7, Bit 3, PWM 11. 90 GPort6_Bit4_PWM4 Port 6, Bit 4, PWM 4.
41 GPort7_Bit2_PWM10 Port 7, Bit 2, PWM 10. 91 GPort6_Bit5_PWM5 Port 6, Bit 5, PWM 5.
42 GPort7_Bit1_PWM9 Port 7, Bit 1, PWM 9. 92 GPort6_Bit6_PWM6 Port 6, Bit 6, PWM 6.
43 GPort7_Bit0_PWM8 Port 7, Bit 0, PWM 8. 93 GPort6_Bit7_PWM7 Port 6, Bit 7, PWM 7.
44 GPort2_Bit2_PWM8/WD Port 2, Bit 2, PWM 8, E
2
Write Disable. 94 DNU DNU = Do Not Use; leave floating.
45 INT 95 GPort0_Bit0_PWM7 Port 0, Bit 0, PWM 7.
46 GPort2_Bit1_PWM12/A2 Port 2, Bit 7, PWM 0, Address 4. 96 DNU DNU = Do Not Use; leave floating.
47 GPort2_Bit0_PWM14/A3 Port 2, Bit 6, PWM 2, Address 5. 97 GPort0_Bit1_PWM5 Port 0, Bit 1, PWM 5.
48 DNU DNU = Do Not Use; leave floating. 98 DNU DNU = Do Not Use; leave floating.
49 DNU DNU = Do Not Use; leave floating. 99 GPort0_Bit2_PWM3 Port 0, Bit 2, PWM 3.
50 DNU DNU = Do Not Use; leave floating. 100 DNU DNU = Do Not Use; leave floating.
CY8C9520A
CY8C9540A
CY8C9560A
Document Number: 38-12036 Rev. *I Page 8 of 32
Figure 4. CY8C9560A 100-Pin Device
[2]
Note
2. DNU = Do Not Use; leave floating.
CY8C9520A
CY8C9540A
CY8C9560A
Document Number: 38-12036 Rev. *I Page 9 of 32
Pin Descriptions
Extendable Soft Addressing
The A0 line defines the corresponding bit of the I
2
C address. This
pin must be pulled up or down. If A0 is a strong pull up or a strong
pull down (wired through 330 or less resistor to Vdd or Vss), then
that is the only address line being specified and the A1-A6 lines
are used as GPIO. If A0 is a weak pull up or a weak pull down
(connected to Vdd or Vss through 75K- 200K ohm resistor), then
A0 is not the only externally defined address bit. There is a pin
assigned to be A1 if it is needed. This pin can be pulled up or
pulled down strong or weak with a resistor. As with A0, the type
of pull determines whether the address bit is the last externally
defined address bit. Differently from A0, A1 is not dedicated as
an address pin. It is only used if A0 is not the only address bit
externally defined. There are also predefined pins for A2, A3, A4,
A5, and A6 that is only used for addressing if needed. The last
address bit in the chain is pulled strong. That way, only the
number of pins needed to assign the address desired for the part
are allocated as address pins, any pins not used for address bits
can be used as GPIO pins. The Table 2 on page 4 defines the
resulting device I
2
C address.
Note: It is not recommended to share pull up/down resistors
between multiple devices.
Interrupt Pin (INT)
The interrupt output (if enabled) is activated if one of these
events occurs:
■ One of the GPIO port pins changes state and the corresponding
bit in the Interrupt Mask register is set low.
■ When a PWM driven by the slowest clock source (367.6 Hz)
and assigned to a pin changes state and the pin’s
corresponding bit in the Interrupt Mask register is set low.
The interrupt line is deactivated when the master device
performs a read from the corresponding Interrupt Status register.
The INT output is active high output and the drive mode of this
pin is strong drive mode.
Write Disable Pin (WD)
If this feature is enabled, ‘0’ allows writes to the EEPROM and
‘1’ blocks any memory writes. This pin is checked immediately
before performing any write to memory. If the EEE bit in the
Enable register is not set (EEPROM disabled) or bit EERO is set
(EEPROM is read-only) then WD line level is ignored.
Note that ‘1’ on this line blocks all commands that perform
operations with EEPROM (see Table 14 on page 14).
This line may be enabled/disabled by bit 1 of the Enable register
(2Dh): ‘1’ enables WD function, ‘0’ disables.
External Reset Pin (XRES)
A full device reset is caused by pulling the XRES pin high. The
XRES pin has an always-on pull down resistor, so it does not
require an external pull down for operation. It can be tied
directly to ground or left open. Behavior after XRES is similar to
POR. When the part is held in reset, all In and Out pins are held
at their default High-Z State.
Working with PWMs
There are four independent PWMs in the CY8C9520A, eight in
the CY8C9540A and sixteen in the CY8C9560A. Each I/O pin
can be configured as a PWM output by writing ‘1’ to the
corresponding bit of the Select PWM register (see Table 7 on
page 12).
The next step of PWM configuration is clock source selection
using the Config PWM registers. There are six available clock
sources: 32 kHz (default), 24 MHz, 1.5 MHz, 93.75 kHz, 367.6
Hz or previous PWM output. (see Figure 5)
Figure 5. Clock Sources
By default, 32 kHz is selected as the PWM clock.
PWM Period registers are used to set the output period:
Allowed values are between 1 and FFh.
The PWM Pulse Width register sets the duration of the PWM
output pulse. Allowed values are between zero and the
(Period-1) value. The duty cycle ratio is computed using thsi
equation:
Divider (1-255)
93.75 kHz
367.6 Hz -
93.75 kHz
1.5 mHz
24 mHz
32 kHz
t
OUT
Period t
CLK
=
DutyCycle
PulseWidth
Period
------------------------------
=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

CY8C9560A-24AXI

Mfr. #:
Buy CY8C9560A-24AXI
Manufacturer:
Cypress Semiconductor
Description:
Interface - I/O Expanders 60BIT IO EXPANDER W/EEPROM
Lifecycle:
New from this manufacturer.
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