CY8C9560A-24AXI Datasheet CY8C9520A-24PVXI, CY8C9560A-24AXI, CY8C9540A-24PVXI | P13-P15

CY8C9520A

CY8C9540A

CY8C9560A

Document Number: 38-12036 Rev. *I Page 13 of 32

Config (29h)

This register selects the clock source for the PWM selected by

the PWM Select register (28h) and interrupt logic.

There are six available clock sources: 32 kHz (default), 24 MHz,

1.5 MHz, 93.75 kHz, 367.6 Hz, or previous PWM output. The

367.6 Hz clock is user programmable. It divides the 93.75 kHz

clock source by the divisor stored in the Divider register (2Ch).

The default divide ratio is 255. (see Table 10 for details). By

default, all PWMs are clocked from 32 kHz.

Each PWM can generate an interrupt at the rising or falling edge

of the output pulse. There is a limitation on the clock source for

a PWM to generate an interrupt. Only the slowest speed source

(programmed to 367.6 Hz) with the divider equal to 255 allows

interrupt generation. Consequently, to create a PWM interrupt, it

is necessary to choose the programmable divider output as the

clock source (write xxxxx100b to Config register (29h)), write 255

to the Divide register (2Ch), and select PWM for pin output (1Ah).

Interrupt status is reflected in the Interrupt Status registers

(10h-17h) and can cause INT line activation if enabled by the

corresponding mask bit in the Interrupt Mask register:

Period Register (2Ah)

This register sets the period of the PWM counter. Allowed values

are between 1 and FFh. The effective output waveform period of

the PWM is:

Pulse Width Register (2Bh)

This register sets the pulse width of the PWM output. Allowed

values are between zero and the (Period - 1) value. The duty

cycle ratio can be computed using the following equation:

Divider Register (2Ch)

This register sets the frequency on the output of the

programmable divider:

Allowed values are between 1 and 255.

Enable Register (2Dh)

The WDE bit configures the write disable pin to operate either as

a GPIO or as WD. It also enables/disables EEPROM operations

(EEE bit) or makes the EEPROM read-only (EERO bit). Bit

assignments are shown in Table 12 on page 13.

Each ’1’ enables the corresponding feature, ’0’ disables.

Writes to this register differ from other registers. The write

sequence to modify the Enable register is as follows:

1. Send device I

C address with bit 0.

2. Send register address 2Dh.

3. Send unlock key - the sequence of three bytes: 43h, 4Dh, 53h;

('C', 'M', 'S' in ASCII bytes).

4. Send new Enable register value.

This write sequence secures the register from accidental

changes. The register can be read without the use of the unlock

key.

By default, EERO and EEPROM (EEE bit) are disabled and WD

line (WDE bit) is set to GPIO (WD disabled).

When performing a burst write operation that crosses this

address increments to 2Eh.

Device ID/Status Register (2Eh)

This register stores device identifiers (2xh/4xh/6xh) and reflects

which settings were loaded during startup, either factory defaults

(FD) or user defaults (UD). By default during startup, the device

attempts to load the user default block. If it is corrupted then

factory defaults are loaded and the low nibble of this register is

set high to inform which set is active. The high nibble is always

equal to 2 for CY8C9520A, 4 for CY8C9540A, and 6 for

CY8C9560A.

This register is read-only.

Table 10. PWM Clock Sources

Config PWM PWM Clock Source

xxxxx000b 32 kHz (default)

xxxxx001b 24 MHz

xxxxx010b 1.5 MHz

xxxxx011b 93.75 kHz

xxxxx100b 367.6 Hz (programmable)

xxxxx101b Previous PWM

Table 11. Period Register

Config PWM PWM Interrupt on

xxxx0xxxb Falling pulse edge (default)

xxxx1xxxb Rising pulse edge

OUT CLK

tPeriodt



Pu lseWidth

DutyCycle

Period



Table 12. Enable Register

Bit 7 6 5 4 3 2 1 0

Function Reserved EERO EEE WDE

Default Reserved 0 0 0

Table 13. Device ID Status Register

Bit 7 6 5 4 3 2 1 0

Function Device Family (2, 4,or 6) Reserved FD/UD

93.75

kHz

Frequency

Divider



CY8C9520A

CY8C9540A

CY8C9560A

Document Number: 38-12036 Rev. *I Page 14 of 32

Watchdog Register (2Fh)

This register controls the internal Watchdog timer. This timer can

trigger a device reset if the device is not responding to I

requests due to misconfiguration. Device operation is not

affected when the Watchdog register = 0. If the I

C master writes

any non zero value to the Watchdog register, the countdown

mechanism is activated and each second the register is

decremented. Upon transition from 1 to 0, the device is rebooted,

which restores user defaults. After reboot, the Watchdog register

value is reset to zero. Any I

C transaction (addressing the

Expander) resets the Watchdog register to the previously stored

value. Any device reboot (caused by a POR or Watchdog) sets

the Watchdog register to zero (turns off the Watchdog feature).

The Watchdog timer can be disabled by writing zero to the

Watchdog register (2Fh) or by using the Reconfigure Device

Cmd (07h).

Note The Watchdog timer is not intended to track precise time

intervals. The timer's frequency can vary in range between –50%

on up to +100%. This variation must be taken into account when

selecting the appropriate value for the Watchdog register.

Command Register (30h)

This register sends commands to the device, including current

configuration as new POR defaults, restore factory defaults,

define POR defaults, read POR defaults, write device

configuration, read device configuration, and reconfigure device

with stored POR defaults. The command set is presented in

Table 14.

Note Registers are not restored in parallel. Do not assume any

particular order to the restoration process.

Commands Description

Store Config to E

POR Defaults Cmd (01h)

The current ports settings (drive modes and output data) and

other configuration registers are saved in the EEPROM by using

the store configuration command (Cmd). These settings are

automatically loaded after the next device power up or if the 07h

command is issued.

Restore Factory Defaults Cmd (02h)

This command replaces the saved user configuration with the

factory default configuration. Current settings are unaffected by

this command. New settings are loaded after the next device

power up or if the 07h command is issued.

Write E

POR Defaults Cmd (03h)

This command sends new power up defaults to the CY8C95xx

without changing current settings unless the 07h command is

issued afterwards. This command is followed by 147 data bytes

according to Table 15. The CRC is calculated as the XOR of the

146 data bytes (00h-91h). If the CRC check fails or an

incomplete block is sent, then the slave responds with a NAK and

the data does not get saved to EEPROM.

To define new POR defaults the user must:

■ Write command 03h

■ Write 146 data bytes with new values of registers

■ Write 1 CRC byte calculated as XOR of previous 146 data

bytes.

Content of the data block is described in Ta ble 15.

Table 14. Available Commands

Command Description

01h Store device configuration to EEPROM POR

defaults

02h Restore Factory Defaults

03h Write EEPROM POR defaults

04h Read EEPROM POR defaults

05h Write device configuration

06h Read device configuration

07h Reconfigure device with stored POR defaults

Table 15. POR Defaults Data Structure

Offset Value

00h–07h Output Port 0–7

08h–0Fh Interrupt mask Port 0–7

10h–17h Select PWM Port 0–7

18h–1Fh Inversion Port 0–7

20h–27h Pin Direction Port 0–7

28h Resistive pull up Drive Mode Port 0

29h Resistive pull down Drive Mode Port 0

2Ah Open drain high Drive Mode Port 0

2Bh Open drain low Drive Mode Port 0

2Ch Strong drive Drive Mode Port 0

2Dh Slow strong drive Drive Mode Port 0

2Eh High impedance Drive Mode Port 0

2Fh–35h Drive Modes Port 1

36h–3Ch Drive Modes Port 2

3Dh–43h Drive Modes Port 3

44h–4Ah Drive Modes Port 4

4Bh–51h Drive Modes Port 5

52h–58h Drive Modes Port 6

59h–5Fh Drive Modes Port 7

60h Config setting PWM0

61h Period setting PWM0

62h Pulse Width setting PWM0

63h–65h PWM1 settings

……

8Dh–8Fh PWM15 settings

90h Divider

91h Enable

92h CRC

CY8C9520A

CY8C9540A

CY8C9560A

Document Number: 38-12036 Rev. *I Page 15 of 32

Read E2 POR Defaults Cmd (04h)

This command reads the POR settings stored in the EEPROM.

To read POR defaults the user must:

■ Write command 04h

■ Read 146 data bytes (see Table 15 on page 14)

■ Read 1 CRC byte.

Write Device Config Cmd (05h)

This command sends a new device configuration to the

CY8C95xx. It is followed by 146 data bytes according to

Table 15. The CRC is calculated as the XOR of the 146 data

bytes (00h-91h). If the CRC check fails or an incomplete block is

sent, then the slave responds with a NAK and the device does

not use the data. This gives the user ‘flat-address-space’ access

to all device settings.

To set the current device configuration the user must:

■ Write command 05h

■ Write 146 data bytes with new values of registers

■ Write 1 CRC byte calculated as XOR of previous 146 data

bytes.

If the CRC check passes, then the device uses the new settings

immediately.

Content of the data block is described in Table 15 on page 14.

Read Device Config Cmd (06h)

This command reads the current device configuration. It gives

the user ‘flat-address-space’ access to all device settings.

To read device configuration the user must:

■ Write command 06h

■ Read 146 data bytes (see Table 15 on page 14).

■ Read 1 CRC byte.

Reconfigure Device Cmd (07h)

This command immediately reconfigures the device with actual

POR defaults from EEPROM. It has the same effect on the

registers as a POR.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

CY8C9560A-24AXI

Mfr. #:

Buy CY8C9560A-24AXI

Manufacturer:

Cypress Semiconductor

Description:

Interface - I/O Expanders 60BIT IO EXPANDER W/EEPROM

Lifecycle:

New from this manufacturer.

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CY8C9560A-24AXI

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