PDF: 09005aef808f912d/Source: 09005aef808f8ccd Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD9C32_64x72A.fm - Rev. F 10/08 EN
11 ©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
Table 11: Idd Specifications and Conditions – 512MB
Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition Symbol -40B -335 -262
-26A/
-265
Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every 2 clock cycles
Idd0 1395 1170 1170 1035 mA
Operating one bank active-read-precharge current:
BL = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle
Idd1 1665 1440 1440 1305 mA
Precharge power-down standby current: All device banks idle;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
Idd2P45454545mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle;
Vin
=
Vref
for DQ, DM, and DQS
Idd2F 495 405 405 360 mA
Active power-down standby current: One device bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
Idd3P 405 315 315 270 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Idd3N 540 450 450 405 mA
Operating burst read current: BL = 2; Continuous burst reads;
One device bank active; Address and control inputs changing once
per clock cycle;
t
CK =
t
CK (MIN); Iout = 0mA
Idd4R 1710 1485 1485 1305 mA
Operating burst write current: BL = 2; Continuous burst writes;
One device bank active; Address and control inputs changing once
per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
Idd4W 1755 1575 1395 1215 mA
Auto refresh current
t
RFC =
t
RFC (MIN)
Idd5 3105 2610 2610 2520 mA
t
RFC = 7.8125µs
Idd5A99909090mA
Self refresh current: CKE ≤ 0.2V
Idd6 45 45 45 45 mA
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs change only during
active READ or WRITE commands
Idd7 4050 3645 3600 3150 mA
