870S208BKLFT Datasheet 870S208BKLF, 870S208BKLFT | P1-P3

DATASHEET

Differential-to-LVCMOS/LVTTL Fanout

Buffer w/Divider and Glitchless Switch

ICS870S208

General Description

The ICS870S208 is a low skew, eight output LVCMOS / LVTTL

Fanout Buffer with selectable divider. The ICS870S208 has two

selectable inputs that accept a variety of differential input types. The

device provides the capability to suppress any glitch at the outputs of

the device during an input clock switch to enhance clock redundancy

in fault tolerant applications. The low impedance LVCMOS outputs

are designed to drive 50series or parallel terminated transmission

lines. The effective fanout can be increased from 8 to 16 by utilizing

the ability of the outputs to drive two series terminated lines. The

divide select inputs, DIV_SELA and DIV_SELB, control the output

frequency of each bank. The output banks can be independently

selected for ÷1 or ÷2 operation. The output enable pins assigned to

each output, support enabling and disabling of each output

individually.

The ICS870S208 is characterized at full 3.3V and 2.5V, and mixed

3.3V/2.5V output operating supply modes. Guaranteed output and

part-to-part skew characteristics make the ICS870S208 ideal for

high performance, single ended applications.

Features

• Eight LVCMOS/LVTTL outputs, (2 banks of 4 outputs)

Each output has individual synchronous output enable

• Two selectable differential CLKx, nCLKx inputs

• Dual differential input pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL

• Maximum output frequency: 250MHz

• Selectable 1 or 2 operation

• Glitchless output behavior during input switch

• Output skew: 120ps (maximum), 3.3V

• Bank skew: 65ps (maximum), 3.3V

• Supply modes:

Core/Output

3.3V/3.3V

2.5V/2.5V

3.3V/2.5V

• 0°C to 70°C ambient operating temperature

• Lead-free (RoHS 6) packaging

Block Diagram Pin Assignment

ICS870S208

32-Lead VFQFN

5mm x 5mm x 0.9mm package body

3.15mm x 3.15mm EPad Size

K Package

Top View

÷1

÷2

Pulldown

Pullup

Pulldown

QA0

DIV_SELA

CLK0

nCLK0

CLK1

CLK_SEL

nCLK1

DIV_SELB

OE_A0

QA1

OE_A1

QA2

OE_A2

QA3

OE_A3

QB0

OE_B0

QB1

OE_B1

QB2

OE_B2

QB3

OE_B3

9 10 11 12 13 14 15

32 31 30 29 28 27 26 25

DIV_SELB

CLK0

nCLK0

CLK_SEL

CLK1

nCLK1

DIV_SELA

OE_B3

OE_B2

OE_B1

OE_B0

OE_A3

OE_A2

OE_A1

OE_A0

GND

QA0

QA1

DDOA

VDDOB

QB0

QB1

GND

QA2

QA3

DDOA

VDDOB

QB2

QB3

GND

ICS870S208 Data Sheet DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH

Pin Descriptions and Characteristics

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Number Name Type Description

1 DIV_SELB Input Pulldown Controls frequency division for Bank B outputs. LVCMOS / LVTTL interface levels.

2 CLK0 Input Pulldown Non-inverting differential clock input.

3 nCLK0 Input Pullup Inverting differential clock input.

Power Power supply pin.

5 CLK_SEL Input Pulldown

Clock select input. When HIGH, selects CLK1, nCLK1 inputs, When LOW, selects

CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.

6 CLK1 Input Pulldown Non-inverting differential clock input.

7 nCLK1 Input Pullup Inverting differential clock input.

8 DIV_SELA Input Pulldown Controls frequency division for Bank A outputs. LVCMOS / LVTTL interface levels.

9, 16, 25, 32 GND Power Power supply ground.

10, 11,

30, 31

QA0, QA1,

QA3, QA2

Output Single-ended Bank A clock outputs. LVCMOS / LVTTL interface levels.

12, 29 V

DDOA

Power Output supply pins for Bank A outputs.

13, 28 V

DDOB

Power Output supply pins for Bank B outputs.

14, 15

26, 27

QB0, QB1,

QB3, QB2

Output Single-ended Bank B clock outputs. LVCMOS / LVTTL interface levels.

17 OE_A0 Input Pullup

Output enable for QA0 output. Active HIGH. If OE pin is LOW, outputs will drive in