ICS870S208BKLF REVISION A APRIL 3, 2013 10 ©2013 Integrated Device Technology, Inc.
ICS870S208 Data Sheet DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Table 5C. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDOA
= V
DDOB
= 2.5V ± 5%, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to V
DDOA, B
/2 of the output.
NOTE 2: Defined as between outputs at the same supply voltage and with equal load conditions. Measured at V
DDOA, B
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of input on each device, the output is measured at V
DDOA, B
/2.
NOTE 5: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
out
Output Frequency 250 MHz
t
PD
Propagation Delay; NOTE 1 2.5 4.1 ns
tsk(o) Output Skew; NOTE 2, 3 140 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 225 ps
tsk(b)
Bank Skew;
NOTE 3, 5
QA[0:3], nQA[0:3] 70 ps
QB[0:3], nQB[0:3] 60 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 150 600 ps
t
EN
Output Enable Time; NOTE 6 10 ns
t
DIS
Output Disable Time; NOTE 6 10 ns
odc Output Duty Cycle 40 60 %
ICS870S208BKLF REVISION A APRIL 3, 2013 11 ©2013 Integrated Device Technology, Inc.
ICS870S208 Data Sheet DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Parameter Measurement Information
3.3V Output Load Test Circuit
3.3V Core/2.5V Output Load Test Circuit
Output Skew
2.5V Output Load Test Circuit
Differential Input Level
Part-to-Part Skew
SCOPE
Qx
GND
V
DD,
1.65V±5%
-1.65V±5%
V
DDOA,
V
DDOB
SCOPE
Qx
LVCMOS
V
DDO
2
GND
2.05V±5%
-1.25V±5%
V
DD
1.25V±5%
V
DDOA,
V
DDOB
Qx
Qy
SCOPE
Qx
GND
1.25V±5%
-1.25V±5%
V
DD,
V
DDOA,
V
DDOB
nCLK[0:1]
CLK[0:1]
V
DD
GND
V
CMR
Cross Points
V
PP
tsk(pp)
V
DDO
2
V
DDO
2
Part 1
Part 2
Qx
Qy
ICS870S208BKLF REVISION A APRIL 3, 2013 12 ©2013 Integrated Device Technology, Inc.
ICS870S208 Data Sheet DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Parameter Measurement Information, continued
Bank Skew
Output Duty Cycle/Pulse Width/Period
Propagation Delay
Output Rise/Fall Time
tsk(b)
V
DDOX
2
V
DDOX
2
QXx
QXy
Where X denotes Bank A or Bank B outputs
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
QA[0:3],
QB[0:3]
t
PD
V
DDO
2
CLK0,
CLK1
QA[0:3],
QB[0:3]
nCLK0,
nCLK1
20%
80%
80%
20%
t
R
t
F
QA[0:3],
QB[0:3]

870S208BKLFT

Mfr. #:
Manufacturer:
Description:
Clock Buffer 8 LVCMOS OUTPUT BUFFER/DIVIDER
Lifecycle:
New from this manufacturer.
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