Philips Semiconductors Product data sheet
SC28L194Quad UART for 3.3 V and 5 V supply voltage
2006 Aug 15
26
Table 26. BRGTCR - BRG Timer Control Register (BRGTCR)
Bit 7 Bit 6:4 Bit 3 Bit 2:0
BRGTCR b, Register control BRGTCR b, Clock selection BRGTCR a, Register control BRGTCR a, Clock selection
0 - Resets the timer register and
holds it stopped
1 - Allows the timer register to
run.
000 - Sclk / 16
001 - Sclk / 32
010 - Sclk/ 64
011 - Sclk / 128
100 - X1
101 - X1 / 2
110 - I/O1b
111 - Gin(1)
0 - Resets the timer register and
holds it stopped.
1 - Allows the timer register to
run.
000 - Sclk / 16
001 - Sclk / 32
010 - Sclk / 64
011 - Sclk / 128
100 - X1
101 - X1 / 2
110 - I/O1a
111 - Gin(0)
Start/Stop control and clock select register for the two BRG
counters. The clock selection is for the input to the counters. It is
that clock divided by the number represented by the BRGTU and
BRGTL the will be used as the 16x clock for the receivers and
transmitters. When the BRG timer Clock is selected for the
receiver(s) or transmitter(s) the receivers and transmitters will
consider it as a 16x clock and further device it by 16. In other words
the receivers and transmitters will always be in the 16x mode of
operation when the internal BRG timer is selected for their clock.
(See equation on page 6.)
Table 27. ICR - Interrupt Control Register
Bit 7 Bits 6:0
Reserved. Set to 0 Upper seven bits of the Arbitration
Threshold
This register provides a single 7 bit field called the interrupt
threshold for use by the interrupt arbiter. The field is interpreted as a
single unsigned integer. The interrupt arbiter will not generate an
external interrupt request, by asserting IRQN, unless the value of
the highest priority interrupt exceeds the value of the interrupt
threshold. If the highest bidder in the interrupt arbitration is lower
than the threshold level set by the ICR, the Current Interrupt
Register, CIR, will contain x’00. Refer to the functional description of
interrupt generation for details on how the various interrupt source
bid values are calculated.
Note: While a watch-dog Timer interrupt is pending, the ICR is not
used and only receiver codes are presented for interrupt arbitration.
This allows receivers with very low count values (perhaps below the
threshold value) to win interrupt arbitration without requiring the user
to explicitly lower the threshold level in the ICR. These bits are the
upper seven (7) bits of the interrupt arbitration system. The lower
three (3) bits represent the channel number.
UCIR - Update CIR
A command based upon a decode of address x’8C. (UCIR is not a
register!) A write (the write data is not important; a “don’t care”) to
this ’register’ causes the Current Interrupt Register to be updated
with the value that is winning interrupt arbitration. The register would
be used in systems that poll the interrupt status registers rather than
wait for interrupts. Alternatively, the CIR is normally updated during
an Interrupt Acknowledge Bus cycle in interrupt driven systems.
Table 28. CIR - Current Interrupt Register
Bits 7:6 Bits 5:3 Bits 2:0
Type Current byte count/type Channel number
00 - other 000 - no interrupt
001 - Change of State
010 - Address
Recognition
011 - Xon/Xoff status
100 - Not used
101 - Break change
110, 111 do not occur
000 = a
001 = b
010 = c
011 = d
.
01 - Transmit
11- Receive w/
errors
10 - Receive w/o
errors
Current count code
0 => 9 or less
characters
1 => 10 characters
.
.
5 => 14 characters
6 => 15 characters
7 => 16
(See also GIBCR)
000 = a
001 = b
010 = c
011 = d.
.
The Current Interrupt Register is provided to speed up the
specification of the interrupting condition in the Quad UART. The
CIR is updated at the beginning of an interrupt acknowledge bus
cycle or in response to an Update CIR command. (see immediately
above) Although interrupt arbitration continues in the background,
the current interrupt information remains frozen in the CIR until
another IACKN cycle or Update CIR command occurs. The LSBs of
the CIR provide part of the addressing for various Global Interrupt
registers including the GIBCR, GICR, GITR and the Global RxFIFO
and TxFIFO FIFO. The host CPU need not generate individual
addresses for this information since the interrupt context will remain
stable at the fixed addresses of the Global Interrupt registers until
the CIR is updated. For most interrupting sources, the data available
in the CIR alone will be sufficient to set up a service routine.
The CIR may be processed as follows:
If CIR[7] = 1, then a receiver interrupt is pending and the count is
CIR[5:3], channel is CIR[2:0]
Else If CIR[6] = 1 then a transmitter interrupt is pending and the
count is CIR[5:3], channel is CIR[2:0]
Else the interrupt is another type, specified in CIR[5:3]
Note: The GIBCR, Global Interrupting Byte Count Register, may be
read to determine an exact character count if 9 or less characters
are indicated in the count field of the CIR.
