Philips Semiconductors Product data sheet
SC28L194Quad UART for 3.3 V and 5 V supply voltage
2006 Aug 15
46
f
SCLK
t
SCLKL
T/RF
SCLK
t
SCLKH
SD00199
Figure 10. SCLK Timing
FC/T
TC/TL
T/RF
SCLK
TC/TH
TC/TO
SD00200
Figure 11. Counter/Timer Baud Rate Clock, External
Frx
Trx
T/RF
TC/TH
TC/TO
Ttx
Ftx
SD00201
Figure 12. Tx/Rx Clock Timing, External
1X DATA CLOCK
t
RXS
t
RXH
t
TXD
RxD
TxD
SD00202
Figure 13. Transmitter and Receiver Timing
Note: CEN must not be active during an IACKN cycle. If CEN is
active IACKN will be ignored and a normal read or write will be
executed according to W_RN.
In the synchronous mode extended IACKN signal cycle will start
another IACKN. (This may not be desired, but is allowed.)
Philips Semiconductors Product data sheet
SC28L194Quad UART for 3.3 V and 5 V supply voltage
2006 Aug 15
47
INDEX
Numbers
1x and 16x modes, Receiver, 8
1x and 16x modes, Transmitter, 8
A
Address Recognition Character Register, 24
ARCR, 24
Asynchronous bus cycle, 5
B
Baud Rate Generator, 6
BCRA, 24
BCRBRK, 24
BCRCOS, 24
BCRx, 24
Bidding Control Register – Address, 24
Bidding Control Register – Break Change, 24
Bidding Control Register – Change of State, 24
Bidding Control Register – Xon, 24
Block diagram, 5
Break, transmission of, 8
BRG Timer Control Register, 26
BRG Timer Reload Registers, Lower, 25
BRG Timer Reload Registers, Upper, 25
BRGTCR, 26
BRGTRL, 25
BRGTRU, 25
C
CEN, 5
Channel Blocks, 6
Channel Status Register, 22
Character Recognition, 6
Character Stripping, 10
CIR, 26
Clock Register, Rx & Tx, 20
Command Register, 20
COMMAND REGISTER TABLE, 22
CR, 20
Crystal oscillator, 5
Current Interrupt Register, 26
D
Description, 2
DESCRIPTION, over all, 5
F
Framing error, 8
G
GCCR, 16
General Purpose Output Clk Register, 29
General Purpose Output Data Register, 29
General Purpose Output Register, 29
General Purpose Output Select Register, 29
General Purpose Pins, 10
GIBCR, 27
GICR, 27
GITR, 27
Global Configuration Control Register (GCCR), 16
Global Interrupting Byte Count Register, 27
Global Interrupting Channel Register, 27
Global Registers, 7, 10
Global RxFIFO Register, 28
Global TxFIFO Register, 28
GPOC, 29
GPOD, 29
GPOR, 29
GPOSR, 29
GRxFIFO, 28
GTxFIFO, 28
H
Host Interface, 5
I
I/O Port Configuration Register, 28
I/O Port Interrupt and Output Register, 28
I/O ports, 9
I/OPCR, 9, 28
I/OPIOR, 28
I/OPIOR register, 9
IACKN, 7
IACKN Cycle, 11
ICR, 26
IMR, 7, 24
Input Port Register, 28
Interrupt Arbitration, 10
Interrupt Control, 7
Interrupt Mask Register, 24
Interrupt priorities, Setting, 11
Interrupt sources, Enabling, 11
Interrupt Status Register, 23
Interrupt Vector Register, 27
Interrupts, Xon/Xoff, 15
IPR, 28
ISR, 7, 23
IVR, 27
M
Minor Modes, 13
Mode control, Xon/Xoff, 15
Mode Register 0, 17
Mode Register 1, 18
Mode Register 2, 19
Mode Registers, Initialization, 16
Modes of Operation, 12
MR0, 17
MR1, 18
MR2, 19
Multidrop mode, 10
O
Overrun error, 9
P
Parity error, 9
Pin configurations, 3
Pin Description, 4
Polling, 11
Philips Semiconductors Product data sheet
SC28L194Quad UART for 3.3 V and 5 V supply voltage
2006 Aug 15
48
R
Receiver, 8
Receiver FIFO, 9, 24
Receiver Status Bits, 8
REGISTER DESCRIPTIONS, 15
Register Map, 30
Register Map, Control, 30, 32
Register Map, Data, 31, 34
Reset Conditons, 36
RxCSR, 20
RxFIFO, 24
S
Sclk, 5
SR, 22
Synchronous bus cycle, 5
System Clock, 6
T
Timing Circuits, 5
Transmitter, 7
Transmitter FIFO, 8, 24
Tx, Status Bits, 7
TxCSR, 20
TxEMT, 7
TxFIFO, 24
TxRDY, 7
U
UCIR, 26
Update CIR, 11, 26
W
Wake-up Mode, 10, 13
Wake-up, Default, 13
Watch–dog Timer, 13
Watch–dog Timer Enable Register, 25
WDTRCR, 25
X
XISR, 25
Xoff Character Register, 24
XoffCR, 24
Xon/Xoff characters, 14
Xon Character Register, 24
Xon/Xoff Interrupt Status Register, 25
Xon/Xoff modes, 15
Xon/Xoff Operation, 14
XonCR, 24

SC28L194A1BE,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC UART QUAD W/FIFO
Lifecycle:
New from this manufacturer.
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