1
DATASHEET
Single Supply/Low Power/256-Tap/SPI Bus, Quad
Digitally-Controlled (XDCP™) Potentiometer
X9251
The X9251 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI bus interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and four nonvolatile
Data Registers that can be directly written to and read by the
user. The content of the WCR controls the position of the wiper.
At power-up, the device recalls the content of the default Data
Registers of each DCP (DR00, DR10, DR20, and DR30) to the
corresponding WCR.
The XDCP can be used as a three terminal potentiometer or as
a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
Four potentiometers in one package
256 resistor taps–0.4% resolution
SPI serial interface for write, read, and transfer operations of
the potentiometer
Wiper resistance: 100Ω typical at V
CC
= 5V
4 Nonvolatile data registers for each potentiometer
Nonvolatile storage of multiple wiper positions
Standby current <5µA max
•V
CC
: 2.7V to 5.5V operation
50kΩ version of total resistance
100 year data retention
Single supply version of X9250
Endurance: 100,000 data changes per bit per register
24 Ld SOIC, 24 Ld TSSOP
•Low power CMOS
Pb-free (RoHS compliant)
POWER UP,
INTERFACE
CONTROL
AND
V
CC
V
SS
SPI
R
H0
R
L0
DCP0
R
W0
A1
SO
SI
CS
HOLD
SCK
WP
WCR0
DR00
DR01
DR02
DR03
R
H1
R
L1
DCP1
R
W1
WCR1
DR10
DR11
DR12
DR13
R
H2
R
L2
DCP2
R
W2
WCR2
DR20
DR21
DR22
DR23
R
H3
R
L3
DCP3
R
W3
WCR3
DR30
DR31
DR32
DR33
A0
Interface
STATUS
FIGURE 1. FUNCTIONAL DIAGRAM
December 3, 2014
FN8166.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9251
2
FN8166.6
December 3, 2014
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Circuit Level Applications
Vary the gain of a voltage amplifier
Provide programmable DC reference voltages for comparators
and detectors
Control the volume in audio circuits
Trim out the offset voltage error in a voltage amplifier circuit
Set the output voltage of a voltage regulator
Trim the resistance in Wheatstone bridge circuits
Control the gain, characteristic frequency and Q-factor in filter
circuits
Set the scale factor and zero point in sensor signal
conditioning circuits
Vary the frequency and duty cycle of timer ICs
Vary the DC biasing of a pin diode attenuator in RF circuits
Provide a control variable (I, V, or R) in feedback circuits
System Level Applications
Adjust the contrast in LCD displays
Control the power level of LED transmitters in communication
systems
Set and regulate the DC biasing point in an RF power amplifier
in wireless systems
Control the gain in audio and home entertainment systems
Provide the variable DC bias for tuners in RF wireless systems
Set the operating points in temperature control systems
Control the operating point for sensors in industrial systems
Trim offset and gain errors in artificial intelligent systems
X9251
3
FN8166.6
December 3, 2014
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Pin Configuration
X9251
(24 LD SOIC/TSSOP)
TOP VIEW
Ordering Information
PART NUMBER (Notes 2, 3)
PART
MARKING
V
CC
LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
X9251US24Z (Note 1
) X9251US Z 5 ±10% 50 0 to +70 24 Ld SOIC (300 mil) M24.3
X9251US24IZ (Note 1
) X9251US ZI -40 to +85 24 Ld SOIC (300 mil) M24.3
X9251UV24Z X9251UV Z 0 to +70 24 Ld TSSOP (4.4mm) M24.173
X9251UV24IZ X9251UV ZI -40 to +85 24 Ld TSSOP (4.4mm) M24.173
X9251US24IZ-2.7 (Note 1
) X9251US ZG 2.7 to 5.5 -40 to +85 24 Ld SOIC (300 mil) M24.3
X9251US24Z-2.7 (Note 1
) X9251US ZG 0 to +70 24 Ld SOIC (300 mil) M24.3
X9251UV24Z-2.7 X9251UV ZF 0 to +70 24 Ld TSSOP (4.4mm) M24.173
X9251UV24IZ-2.7 (Note 1
) X9251UV ZG -40 to +85 24 Ld TSSOP (4.4mm) M24.173
NOTES:
1. Add "T1" suffix for tape and reel.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9251
. For more information on MSL, please see tech brief TB363
SO
A0
R
W3
NC
V
CC
R
L0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
R
L2
R
H2
R
W2
NC
V
SS
R
W1
R
H1
R
L1
X9251
R
H3
14
13
11
12
R
L3
R
H0
R
W0
CS
A1
SI
WP
Pin Descriptions
PIN
(SOIC) SYMBOL FUNCTION
1 SO Serial Data Output for SPI bus
2 A0 Device Address for SPI bus (see Note 4
)
3R
W3
Wiper Terminal of DCP3
4R
H3
High Terminal of DCP3
5R
L3
Low Terminal of DCP3
7V
CC
System Supply Voltage
8R
L0
Low Terminal of DCP0
9R
H0
High Terminal of DCP0
10 R
W0
Wiper Terminal of DCP0
11 CS
SPI bus. Chip Select active low input
12 WP
Hardware Write Protect - active low
13 SI Serial Data Input for SPI bus
14 A1 Device Address for SPI bus (see Note 4
)
15 R
L1
Low Terminal of DCP1
16 R
H1
High Terminal of DCP1
17 R
W1
Wiper Terminal of DCP1
18 V
SS
System Ground
20 R
W2
Wiper Terminal of DCP2
21 R
H2
High Terminal of DCP2
22 R
L2
Low Terminal of DCP2
23 SCK Serial Clock for SPI bus
24 HOLD
Device select. Pauses the SPI serial bus.
6, 19 NC No Connect
NOTE:
4. A0 and A1 device address pins must be tied to a logic level.

X9251UV24Z-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs QD DCP 50KOHM 256 TAPS SPI
Lifecycle:
New from this manufacturer.
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