X9251
4
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Functional Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is shifted
out on this pin. Data is clocked out by the falling edge of the
serial clock.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses and
data to be written to the device registers are input on this pin.
Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the X9251.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the device.
Once the part is selected and a serial sequence is underway,
HOLD
may be used to pause the serial communication with the
controller without resetting the serial sequence. To pause, HOLD
must be brought LOW while SCK is LOW. To resume
communication, HOLD
is brought HIGH, again while SCK is LOW.
If the pause feature is not used, HOLD should be held HIGH at all
times.
DEVICE ADDRESS (A1 AND A0)
The address inputs are used to set the two least significant bits of
the slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
communication with the X9251. Device pins A1 and A0 must be
tied to a logic level which specifies the internal address of the
device, see Figures 3
, 4, 5, 6 and 7.
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the SO pin is at
high impedance, and (unless an internal write cycle is underway)
the device is in the standby state. CS
LOW enables the X9251,
placing it in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS
is required prior to
the start of any operation.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal connections on
a mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R
H
and R
L
such that R
H0
and R
L0
are the
terminals of DCP0 and so on.
R
W
The wiper pins are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R
W
such that R
W0
is the terminals of DCP0
and so on.
Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is the
system ground.
Other Pins
NO CONNECT
No connect pins should be left floating. These pins are used for
Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin, when LOW, prevents nonvolatile writes to the Data
Registers.
Principles of Operation
The X9251 is an integrated circuit incorporating four DCPs and
their associated registers and counters, and a serial interface
providing direct communication between a host and the
potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(R
H
and R
L
pins). The RW pin is an intermediate node, equivalent
to the wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is controlled by
an 8-bit volatile Wiper Counter Register (WCR).
X9251
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December 3, 2014
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One of Four Potentiometers
Power-Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the potentiometer
pins provided that V
CC
is always more positive than or equal to
V
H
, V
L
, and V
W
(i.e., V
CC
V
H
, V
L
, V
W
). The V
CC
ramp rate
specification is always in effect.
Wiper Counter Register (WCR)
The X9251 contains four Wiper Counter Registers, one for each
potentiometer. The Wiper Counter Register can be envisioned as
a 8-bit parallel and serial load counter with its outputs decoded
to select one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it can be
modified one step at a time by the Increment/Decrement
instruction (see
Instruction Format” on page 10 for more
details). Finally, it is loaded with the contents of its Data Register
zero (DR#0) upon power-up (see Figure 2
).
The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered down. Although the
register is automatically loaded with the value in DR#0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR#0 value into the WCR#.
Data Registers (DR)
Each of the four DCPs has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four Data Registers and the
associated Wiper Counter Register. All operations changing data
in one of the Data Registers is a nonvolatile operation and takes
a maximum of 10ms.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper positions or data
(0 ~ 255).
Status Register (SR)
This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.
WIP = 1, indicates that high-voltage write cycle is in progress.
WIP = 0, indicates that no high-voltage write cycle is in
progress.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
8 8
COUNTER
IF WCR = 00[H] then R
W
is closest to R
L
IF WCR = FF[H] then R
W
is closest to R
H
WIPER
(WCR#)
#: 0, 1, 2, or 3
DR#2
DR#1
DR#3
- - -
DECODE
DCP
CORE
R
W
R
H
R
L
FIGURE 2. DETAILED POTENTIOMETER BLOCK DIAGRAM
TABLE 1. WIPER COUNTER REGISTER, WCR (8-BIT), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
(MSB) (LSB)
TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(MSB) (LSB)
X9251
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Serial Interface
The X9251 supports the SPI interface hardware conventions. The
device is accessed via the SI input with data clocked in, on the
rising SCK. CS
must be LOW and the HOLD and WP pins must be
HIGH during the entire operation.
The SO and SI pins can be connected together, since they have
three-state outputs. This can help to reduce system pin count.
Identification Byte
The first byte sent to the X9251 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The most
significant four bits of the Identification Byte are a Device Type
Identifier, ID[3:0]. For the X9251, this is fixed as 0101 (refer to
Table 3
).
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0, A1 is
the logic value at the input pin A1, and A0 is the logic value at the
input pin A0. Only the device which Slave Address matches the
incoming bits sent by the master executes the instruction. The A1
and A0 inputs can be actively driven by CMOS input signals or
tied to V
CC
or V
SS
.
Instruction Byte
The next byte sent to the X9251 contains the instruction and
register pointer information. The four most significant bits are
used to provide the instruction opcode (I[3:0]). The RB and RA
bits point to one of the four Data Registers of each associated
XDCP. The least two significant bits point to one of four Wiper
Counter Registers or DCPs. The format is shown below in Table 4
.
TABLE 3. IDENTIFICATION BYTE FORMAT
DEVICE TYPE IDENTIFIER SLAVE ADDRESS
ID3 ID2 ID1 ID0 A3 A2 A1 A0
010100Pin A1
Logic Value
Pin A0
Logic Value
(MSB) (LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
INSTRUCTION OPCODE REGISTER SELECTION
DCP SELECTION
(WCR SELECTION)
I3 I2 I1 I0 RB RA P1 P0
(MSB) (LSB)
Data Register Selection
REGISTER RB RA
DR#0 0 0
DR#1 0 1
DR#2 1 0
DR#3 1 1
#: 0, 1, 2, or 3
TABLE 5. INSTRUCTION SET
INSTRUCTION
INSTRUCTION SET
OPERATIONI3 I2 I1 I0 RB RA P1 P0
Read Wiper Counter Register 1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register
pointed to by P1, P0
Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter Register
pointed to by P1, P0
Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by
P1, P0 and RB, RA
Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to by P1,
P0 and RB, RA
XFR Data Register to
Wiper Counter Register
1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to by
P1, P0 and RB, RA to its associated Wiper Counter
Register

X9251UV24Z-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs QD DCP 50KOHM 256 TAPS SPI
Lifecycle:
New from this manufacturer.
Delivery:
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