X9251
7
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Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
Read Wiper Counter Register – read the current wiper position
of the selected potentiometer
Write Wiper Counter Register – change current wiper position
of the selected potentiometer
Read Data Register – read the contents of the selected Data
Register
Write Data Register – write a new value to the selected Data
Register
Read Status – this command returns the contents of the WIP
bit which indicates if the internal write cycle is in progress
The basic sequence of the three-byte instructions is illustrated in
Figure 4
. These three-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM, with the
static RAM controlling the wiper position. The response of the
wiper to this action is delayed by t
WRL
. A transfer from the WCR
(current wiper position), to a Data Register is a write to
nonvolatile memory and takes a minimum of t
WR
to complete.
The transfer can occur between one of the four potentiometer’s
WCR, and one of its associated registers, DRs; or it may occur
globally, where the transfer occurs between all potentiometers
and one associated register. The Read Status Register instruction
is the only unique format (see Figure 6
).
Four instructions require a two-byte sequence to complete. These
instructions transfer data between the host and the X9251;
either between the host and one of the data registers or directly
between the host and the Wiper Counter Register. These
instructions are:
XFR Data Register to Wiper Counter Register – This transfers
the contents of one specified Data Register to the associated
Wiper Counter Register.
XFR Wiper Counter Register to Data Register – This transfers
the contents of the specified Wiper Counter Register to the
specified associated Data Register.
Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
Increment/Decrement Command
The final command is Increment/Decrement (see Figures 7 and 8).
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9251 has
responded with an Acknowledge, the master can clock the
selected wiper up and/or down in one segment steps, thereby
providing a fine tuning capability to the host. For each SCK clock
pulse (t
HIGH
) while SI is HIGH, the selected wiper moves one
wiper position towards the R
H
terminal. Similarly, for each SCK
clock pulse while SI is LOW, the selected wiper moves one wiper
position towards the R
L
terminal. A detailed illustration of the
sequence and timing for this operation are shown. See
Instruction Format” on page 10 for more details.
XFR Wiper Counter
Register to Data Register
1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register
pointed to by P1, P0 to the Data Register pointed to
by RB, RA
Global XFR Data Registers to Wiper
Counter Registers
0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed to
by RB, RA of all four pots to their respective Wiper
Counter Registers
Global XFR Wiper Counter Registers
to Data Register
1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter Registers
to their respective data Registers pointed to by RB, RA
of all four pots
Increment/Decrement
Wiper Counter Register
0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch
pointed to by P1, P0
NOTE: 1/0 = data is one or zero
TABLE 5. INSTRUCTION SET (Continued)
INSTRUCTION
INSTRUCTION SET
OPERATIONI3 I2 I1 I0 RB RA P1 P0
X9251
8
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December 3, 2014
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ID3 ID2 ID1 ID0 0
A1 A0
I3
I2
I1
RB RA P0
SCK
SI
CS
0101
DEVICE ID
INTERNAL
INSTRUCTION
OPCODE
ADDRESS
REGISTER
0
I0
P1
ADDRESS
DCP/WCR
ADDRESS
0
0
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
0101
A1 A0
I3 I2
I1
I0
RB RA P0
SCK
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
DEVICE ID
INTERNAL
INSTRUCTION
OPCODE
ADDRESS
REGISTER
ADDRESS
DCP/WCR
ADDRESS
00
P1
DATA FOR WCR[7:0] OR DR[7:0]
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
0101
A1 A0
I3
I2
I1
I0
RB RA P0
SCK
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
DEVICE ID
INTERNAL
INSTRUCTION
OPCODE
ADDRESS
REGISTER
ADDRESS
DCP/WCR
ADDRESS
00
P1
WCR[7:0]
S0
X
X
X
XX
XX
X
DON’T CARE
OR
DATA REGISTER BIT [7:0]
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
X9251
9
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December 3, 2014
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WIP
STATUS
BIT
0 101
A1 A0
I3
I2
I1
I0
RB RA
P0
SCK
SI
CS
00ID3 ID2 ID1 ID0
DEVICE ID
INTERNAL
INSTRUCTION
OPCODE
ADDRESS
REGISTER
ADDRESS
POT/WCR
ADDRESS
00
P1
0
0
0
00
00
101
1
FIGURE 6. THREE-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTER)
0101
A1 A0
I3I2
I1
I0
RB RA P0
SCK
SI
CS
00
ID3 ID2 ID1 ID0
DEVICE ID
INTERNAL
INSTRUCTION
OPCODE
ADDRESS
REGISTER
ADDRESS
POT/WCR
ADDRESS
00
P1
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
FIGURE 7. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
SCK
SI
R
W
INC/DEC CMD ISSUED
t
WRID
VOLTAGE OUT
FIGURE 8. INCREMENT/DECREMENT TIMING SPEC

X9251UV24Z-2.7

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs QD DCP 50KOHM 256 TAPS SPI
Lifecycle:
New from this manufacturer.
Delivery:
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