AD7856
–12–
REV. A
STATUS REGISTER
The arrangement of the Status Register is shown below. The status register is a read only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
Figure 6. Flowchart for Reading the Status Register
MSB
ZERO BUSY SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0
RDSLT1 RDSLT0 2/3 MODE X CALMD CALSLT1 CALSLT0 STCAL
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
Bit Mnemonic Comment
15 ZERO This bit is always 0.
14 BUSY Conversion/Calibration Busy Bit. When this bit is 1 it indicates that there is a conversion or
calibration in progress. When this bit is 0, there is no conversion or calibration in progress.
13 SGL/DIFF These four bits indicate the channel which is selected for conversion (see Table III).
12 CH2
11 CH1
10 CH0
9 PMGT1 Power management bits. These bits, along with the SLEEP pin, will indicate if the part is in a
8 PMGT0 power-down mode or not. See Table VI for description.
7 RDSLT1 Both of these bits are always 1, indicating it is the status register which is being read (see Table II).
6 RDSLT0
52/3 MODE Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at 1,
the device is in Interface Mode 1. This bit is reset to 0 after every read cycle.
4 X Don’t care bit.
3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self calibration is selected, and a 1 in this bit
indicates a system calibration is selected (see Table IV).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a
1 CALSLT0 calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and
0 STCAL CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing
(see section on the Calibration Registers for more details).
AD7856
–13–REV. A
CALIBRATION REGISTERS
The AD7856 has ten calibration registers in all, eight for the
DAC, one for the offset and one for gain. Data can be written
to or read from all ten calibration registers. In self- and system
calibration the part automatically modifies the calibration regis-
ters; only if the user needs to modify the calibration registers
should an attempt be made to read from and write to the cali-
bration registers.
Addressing the Calibration Registers
The calibration selection bits in the control register CALSLT1
and CALSLT0 determine which of the calibration registers are
addressed (see Table V). The addressing applies to both the
read and write operations for the calibration registers. The user
should not attempt to read from and write to the calibration
registers at the same time.
Table V. Calibration Register Addressing
CALSLT1 CALSLT0 Comment
0 0 This combination addresses the
Gain (1), Offset (1) and DAC Reg-
isters (8). Ten registers in total.
0 1 This combination addresses the
Gain (1) and Offset (1) Registers.
Two registers in total.
1 0 This combination addresses the
Offset Register. One register in
total.
1 1 This combination addresses the
Gain Register. One register in total.
Writing to/Reading from the Calibration Registers
For writing to the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits.
For reading from the calibration registers a write to the control
register is required to set the CALSLT0 and CALSLT1 bits,
but also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-
dresses the calibration registers for reading). The calibration
register pointer is reset upon writing to the control register
setting the CALSLT1 and CALSLT0 bits, or upon completion
of all the calibration register write/read operations. When reset,
it points to the first calibration register in the selected write/
read sequence. The calibration register pointer will point to the
gain calibration register upon reset in all but one case, this case
being where the offset calibration register is selected on its own
(CALSLT1 = 1, CALSLT0 = 0). Where more than one cali-
bration register is being accessed the calibration register pointer
will be automatically incremented after each calibration register
write/read operation. The order in which the ten calibration
registers are arranged is shown in Figure 7. The user may abort
at any time before all the calibration register write/read opera-
tions are completed, and the next control register write opera-
tion will reset the calibration register pointer. The flowchart in
Figure 8 shows the sequence for writing to the calibration regis-
ters and Figure 9 for reading.
CAL REGISTER
ADDRESS POINTER
GAIN REGISTER
OFFSET REGISTER
DAC 1ST MSB REGISTER
DAC 8TH MSB REGISTER
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(1)
(2)
(3)
(10)
CALIBRATION REGISTERS
CALIBRATION REGISTER
ADDRESS POINTER
POSITION IS DETERMINED
BY THE NUMBER OF
CALIBRATION REGISTERS
ADDRESSED AND THE
NUMBER OF READ/WRITE
OPERATIONS
Figure 7. Calibration Register Arrangements
When reading from the calibration registers there will always be
two leading zeros for each of the registers. When operating in
Serial Interface Mode 1 the read operations to the calibration
registers cannot be aborted. The full number of read operations
must be completed (see section on Serial Interface Mode 1
Timing for more detail).
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0
AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
WRITE TO CAL REGISTER
(ADDR1 = 1, ADDR0 = 0)
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
WRITE
OPERATION
OR
ABORT
?
FINISHED
YES
NO
Figure 8. Flowchart for Writing to the Calibration
Registers
AD7856
–14–
REV. A
START
WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,
RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11
CAL REGISTER POINTER IS
AUTOMATICALLY RESET
READ CAL REGISTER
CAL REGISTER POINTER IS
AUTOMATICALLY INCREMENTED
LAST
REGISTER
READ
OPERATION
OR
ABORT
?
FINISHED
YES
NO
Figure 9. Flowchart for Reading from the Calibration
Registers
Adjusting the Offset Calibration Register
The offset calibration register contains 16 bits, two leading zeros
and 14 data bits. By changing the contents of the offset register
different amounts of offset on the analog input signal can be
compensated for. Increasing the number in the offset calibration
register compensates for negative offset on the analog input
signal, and decreasing the number in the offset calibration regis-
ter compensates for positive offset on the analog input signal.
The default value of the offset calibration register is approxi-
mately 0010 0000 0000 0000. This is not an exact value, but
the value in the offset register should be close to this value. Each
of the 14 data bits in the offset register is binary weighted: the
MSB has a weighting of 5% of the reference voltage, the MSB-1
has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,
and so on down to the LSB, which has a weighting of 0.0006%.
This gives a resolution of
approximately ±0.0006% of V
REF
.
More accurately the resolution is ±(0.05 × V
REF
)/2
13
volts =
±0.015 mV, with a 2.5 V reference. The maximum specified
offset that can be compensated for is ±3.75% of the reference
voltage but is typically ±5%, which equates to ±125 mV with a
2.5 V reference and ±250 mV with a 5 V reference.
Q. If a +20 mV offset is present in the analog input signal and the
reference voltage is 2.5 V, what code needs to be written to the
offset register to compensate for the offset?
A. 2.5 V reference implies that the resolution in the offset regis-
ter is 5% × 2.5 V/2
13
= 0.015 mV. +20 mV/0.015 mV =
1310.72; rounding to the nearest number gives 1311. In
binary terms this is 0101 0001 1111. Therefore, decrease the
offset register by 0101 0001 1111.
This method of compensating for offset in the analog input
signal allows for fine tuning the offset compensation. If the
offset on the analog input signal is known, there will be no need
to apply the offset voltage to the analog input pins and do a
system calibration. The offset compensation can take place in
software.
Adjusting the Gain Calibration Register
The gain calibration register contains 16 bits, two leading 0s
and 14 data bits. The data bits are binary weighted as in the
offset calibration register. The gain register value is effectively
multiplied by the analog input to scale the conversion result
over the full range. Increasing the gain register compensates for
a smaller analog input range and decreasing the gain register
compensates for a larger input range. The maximum analog
input range for which the gain register can compensate is
1.01875 times the reference voltage; the minimum input range
is 0.98125 times the reference voltage.

AD7856KRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V SGL-Supply 8-Ch 14B 285kSPS
Lifecycle:
New from this manufacturer.
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