AD7856
–6–
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7856 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . ␣ –0.3 V to +7 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . ␣ –0.3 V to +7 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . ␣ –0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DV
DD
+ 0.3 V
REF
IN
/REF
OUT
to AGND . . . . . . . . . ␣ –0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . ±10 mA
Operating Temperature Range Commercial
A Version . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +105°C
K Version . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W
Lead Temperature, (Soldering, 10 secs) . . . . . . . . . +260°C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . 75°C/W (SOIC) 115°C/W (SSOP)
θ
JC
Thermal Impedance . . 25°C/W (SOIC) 35°C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
PIN CONFIGURATIONS
(DIP, SOIC AND SSOP)
13
16
15
14
24
23
22
21
20
19
18
17
TOP VIEW
(Not to Scale)
12
11
10
9
8
1
2
3
4
7
6
5
AD7856
CONVST
DIN
CLKIN
SCLK
SYNC
BUSY
SLEEP
REF
IN
/REF
OUT
DV
DD
DGND
DOUT
AV
DD
AGND
C
REF1
C
REF2
AIN1
AIN2
AIN7
AIN8
CAL
AIN3
AIN4
AIN6
AIN5
ORDERING GUIDE
Linearity
Error Package
Model (LSB)
1
Options
2
AD7856AN ±2 typ N-24
AD7856AR ±2 typ R-24
AD7856KR ±2 R-24
AD7856ARS ±2 typ RS-24
EVAL-AD7856CB
3
EVAL-CONTROL BOARD
4
NOTES
1
Linearity error here refers to integral linearity error.
2
N = Plastic DIP; R = SOIC; RS = SSOP.
3
This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.
4
This board is a complete unit allowing a PC to control and communicate with
all Analog Devices evaluation boards ending in the CB designators.
AD7856
–7–REV. A
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
1 CONVST Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode
and starts conversion. When this input is not used, it should be tied to DV
DD
.
2 BUSY Busy Output. The busy output is triggered high by the falling edge of␣ CONVST or rising edge of CAL,
and remains high until conversion is completed. BUSY is also used to indicate when the AD7856 has
completed its on-chip calibration sequence.
3 SLEEP Sleep Input/Low Power Mode. A Logic 0 initiates a sleep, and all circuitry is powered down, including
the internal voltage reference, provided there is no conversion or calibration being performed. Calibration
data is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
4 REF
IN
/REF
OUT
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is
the reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and
this appears at the pin. This pin can be overdriven by an external reference or can be taken as high as
AV
DD
. When this pin is tied to AV
DD,
or when an externally applied reference approaches AV
DD,
the
C
REF1
pin should also be tied to AV
DD
.
5AV
DD
Analog Positive Supply Voltage, +5.0 V ± 5%.
6 AGND Analog Ground. Ground reference for track/hold, reference and DAC.
7C
REF1
Reference Capacitor (0.1 µF Multilayer Ceramic in parallel with a 470 nF NPO type). This external
capacitor is used as a charge source for the internal DAC. The capacitor should be tied between the pin
and AGND.
8C
REF2
Reference Capacitor (0.01 µF Multilayer Ceramic). This external capacitor is used in conjunction with
the on-chip reference. The capacitor should be tied between the pin and AGND.
9–16 AIN1–AIN8 Analog Inputs. Eight analog inputs that can be used as eight single-ended inputs (referenced to AGND)
or four pseudo-differential inputs. Channel configuration is selected by writing to the control register.
Both the positive and negative inputs cannot go below AGND or above AV
DD
at any time. Also the posi-
tive input cannot go below the negative input. See Table III for channel selection.
17 CAL Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A falling edge on this pin
resets all calibration control logic and initiates a calibration on its rising edge. There is the option of
connecting a 10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on
power-up. This input overrides all other internal operations. If the autocalibration is not required, this
pin should be tied to a logic high.
18 DV
DD
Digital Supply Voltage, +5.0 V ± 5%.
19 DGND Digital Ground. Ground reference point for digital circuitry.
20 DOUT Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
21 DIN Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can
act as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).
22 CLKIN Master clock signal for the device (A Grade: 6 MHz; K Grade: 4 MHz). Sets the conversion and calibra-
tion times.
23 SCLK Serial Port Clock. Logic Input. The user must provide a serial clock on this input.
24 SYNC Frame Sync. Logic Input. This pin is level triggered active low and frames the serial clock for the read
and write operations (see Table IX).
AD7856
–8–
REV. A
TERMINOLOGY
1
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Unadjusted Error
This is the deviation of the actual code from the ideal code
taking all errors into account (Gain, Offset, Integral Nonlinearity
and other errors) at any point along the transfer function.
Unipolar Offset Error
This is the deviation of the first code transition (00␣ .␣ .␣ .␣ 000 to
00␣ .␣ .␣ .␣ 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB).
Positive Full-Scale Error
This is the deviation of the last code transition from the ideal
AIN(+) voltage (AIN(–) + Full Scale – 1.5 LSB) after the offset
error has been adjusted out.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of crosstalk between
the channels. It is measured by applying a full-scale 25 kHz
signal to the other seven channels and determining how much
that signal is attenuated in the channel of interest. The figure
given is the worst case for all channels.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode and the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f
S
/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 14-bit converter, this is 86 dB.
NOTE
1
AIN(+) refers to the positive input of the pseudo-differential pair, and AIN(–)
refers to the negative analog input of the pseudo-differential pair or to AGND
depending on the channel configuration.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7856, it is defined as:
THD (dB) =20 log
V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Testing is performed using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used. In
this case, the second order terms are usually distanced in fre-
quency from the original sine waves, while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals expressed in dBs.
Full Power Bandwidth
The Full Power Bandwidth (FPBW) of the AD7856 is that
frequency at which the amplitude of the reconstructed (using
FFTs) fundamental (neglecting harmonics and SNR) is reduced
by 3 dB for a full-scale input.

AD7856KRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V SGL-Supply 8-Ch 14B 285kSPS
Lifecycle:
New from this manufacturer.
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