AD7856
–18–
REV. A
PERFORMANCE CURVES
The following performance curves apply to Mode 2 operation
only. If a conversion is initiated in software, then a slight degra-
dation in SNR can be expected when in Mode 2 operation. As
the sampling instant cannot be guaranteed internally, nonequi-
distant sampling will occur, resulting in a rise in the noise floor.
Initiating conversions in software is not recommended for Mode
1 operation.
Figure 18 shows a typical FFT plot for the AD7856 at 190 kHz
sample rate and 10 kHz input frequency.
FREQUENCY –kHz
–115
010
–95
–75
–55
–35
–15
20 30 40 50 60 70 80 90
4096 POINT FFT
F
SAMPLE
= 190.476 kHz
F
IN
= 10.091 kHz
SNR = 79.2dB
Figure 18. FFT Plot
Figure 19 shows the SNR vs. Frequency for 5 V supply and a
4.096 external reference (5 V reference is typically 1 dB better
performance).
INPUT FREQUENCY – kHz
79
75
0 16620 50 120 140
78
77
76
S(N+D) RATIO – dB
10 80 100
Figure 19. SNR vs. Frequency
Figure 20 shows the Power Supply Rejection Ratio versus Fre-
quency for the part. The Power Supply Rejection Ratio is de-
fined as the ratio of the power in ADC output at frequency f to
the power of a full-scale sine wave.
PSRR (dB) = 10 log (Pf/Pfs)
Pf = Power at frequency f in ADC output, Pfs = power of a
full-scale sine wave. Here a 100 mV peak-to-peak sine wave is
coupled onto the AV
DD
supply while the digital supply is left
unaltered.
INPUT FREQUENCY – kHz
–72
–74
–90
0.91 10013.4 25.7 38.3 50.3
–76
–78
–80
–88
PSRR – dB
–82
–84
–86
63.5 74.8 87.4
AV
DD
= DV
DD
= 5.0V
100mV p-p SINEWAVE ON AV
DD
REF
IN
= 4.098 EXT REFERENCE
Figure 20. PSRR vs. Frequency
POWER-DOWN OPTIONS
The AD7856 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate. The power management options are selected by
programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the SLEEP pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. The AD7856 can be fully or partially
powered down. When fully powered down, all the on-chip cir-
cuitry is powered down and I
DD
is 1 µA typ. If a partial power-
down is selected, then all the on-chip circuitry except the reference
is powered down and I
DD
is 400 µA typ. The choice of full or par-
tial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is
discussed in the next section–Power-Up Times. However, a
partial power-down does allow the on-chip reference to be used
externally even though the rest of the AD7856 circuitry is pow-
ered down. It also allows the AD7856 to be powered up faster
after a long power-down period when using the on-chip refer-
ence (See Power-Up Times–Using On-Chip Reference).
When using the SLEEP pin, the power management bits PMGT1
and PMGT0 should be set to zero (default status on power-up).
Bringing the SLEEP pin logic high ensures normal operation,
and the part does not power down at any stage. This may be
necessary if the part is being used at high throughput rates when
it is not possible to power down between conversions. If the user
wishes to power down between conversions at lower throughput
rates (i.e. <100 kSPS for the AD7856) to achieve better power
performances, then the SLEEP pin should be tied logic low.
If the power-down options are to be selected in software only,
then the SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down Be-
tween Conversions can be selected.
AD7856
–19–REV. A
A combination of hardware and software selection can also be
used to achieve the desired effect.
Table VI.␣ Power Management Options
PMGT1 PMGT0 SLEEP
Bit Bit Pin Comment
0 0 0 Full Power-Down Between
Conversions (HW/SW)
0 0 1 Full Power-Up (HW/SW)
0 1 X Normal Operation
(Independent of the SLEEP
Pin)
1 0 X Full Power-Down (SW)
1 1 X Partial Power-Down Between
Conversions
NOTE
HW = Hardware Selection; SW = Software Selection.
POWER-UP TIMES
Using an External Reference
When the AD7856 is powered up, the part is powered up from
one of two conditions. First, when the power supplies are ini-
tially powered up and, secondly, when the part is powered up
from either a hardware or software power-down (see last section).
When AV
DD
and DV
DD
are powered up, the AD7856 should be
left idle for approximately 42 ms (6 MHz CLK) to allow for the
autocalibration if a 10 nF cap is placed on the CAL pin, (see
Calibration section). During power-up the functionality of the
SLEEP pin is disabled, i.e., the part will not power down until
the end of the calibration if SLEEP is tied logic low. The auto-
calibration on power-up can be disabled if the CAL pin is tied to
a logic high. If the autocalibration is disabled, then the user must
take into account the time required by the AD7856 to power-up
before a self-calibration is carried out. This power-up time is the
time taken for the AD7856 to power up when power is first
applied (300 µs) typ) or the time it takes the external reference
to settle to the 14-bit level–whichever is the longer.
AUTO POWER
DOWN AFTER
CONVERSION
AUTO CAL ON
POWER-UP
AV
DD
DV
DD
AIN(+)
AIN(–)
C
REF1
C
REF2
SLEEP
DIN
DOUT
SYNC
CONVST
AGND
DGND
CLKIN
SCLK
REF
IN
/REF
OUT
AD7856
ANALOG
SUPPLY
+5V
0.1mF
0.1mF10mF
0.1mF
0.01mF
MASTER CLOCK
INPUT
CONVERSION
START INPUT
SERIAL DATA OUTPUT
0.1mF
CAL
0.01mF
INTERNAL
REFERENCE
0V TO 2.5V
INPUT
4/6MHz OSCILLATOR
SERIAL CLOCK
INPUT
100kHz PULSE GENERATOR
OPTIONAL
EXTERNAL
REFERENCE
REF-192
SERIAL DATA INPUT
LOW POWER
mC/mP
CURRENT, I = 12mA TYP
Figure 21. Typical Low Power Circuit
AD7856
–20–
REV. A
internal switch opens to provide a high impedance discharge
path for the reference capacitor during power-down—see Figure
23. An added advantage of the low charge leakage from the
reference capacitor during power-down is that even though the
reference is being powered down between conversions, the
reference capacitor holds the reference voltage to within
0.5 LSBs with throughput rates of 100 samples/second and over
with a full power-down between conversions. A high input im-
pedance op amp like the AD707 should be used to buffer this
reference capacitor if it is being used externally. Note, if the
AD7856 is left in its power-down state for more than 100 ms,
the charge on C
REF
will start to leak away and the power-up
time will increase. If this long power-up time is a problem, the
user can use a partial power-down for the last conversion so the
reference remains powered up.
AD7856
REF
IN
/REF
OUT
EXTERNAL
CAPACITOR
SWITCH OPENS
DURING POWER-DOWN
BUF
ON-CHIP
REFERENCE
TO OTHER
CIRCUITRY
Figure 23. On-Chip Reference During Power-Down
POWER VS. THROUGHPUT RATE
The main advantage of a full power-down after a conversion is
that it significantly reduces the power consumption of the part
at lower throughput rates. When using this mode of operation
the AD7856 is only powered up for the duration of the conver-
sion. If the power-up time of the AD7856 is taken to be 5 µs
and it is assumed that the current during power up is 12 mA
typ, then power consumption as a function of throughput can
easily be calculated. The AD7856 has a conversion time of
3.5 µs with a 6 MHz external clock. This means the AD7856
consumes 12 mA typ, (or 60 mW typ V
DD
= 5 V) for 8.5 µs in
every conversion cycle if the device is powered down at the end
of a conversion. If the throughput rate is 1 kSPS, the cycle time
is 1000 µs and the average power dissipated during each cycle is
(8.5/1000) × (60 mW) = 510 µW. The graph, Figure 24, shows
the power consumption of the AD7856 as a function of through-
put. Table VII lists the power consumption for various through-
put rates.
Table VII. Power Consumption vs. Throughput
Throughput Rate Power
1 kSPS 510 µW
10 kSPS 5.1 mW
The AD7856 powers up from a full hardware or software
power-down in 5 µs typ. This limits the throughput which the
part is capable of to 93 kSPS for the K grade and 113 kSPS for
the A grade when powering down between conversions. Figure
22 shows how power-down between conversions is implemented
using the CONVST pin. The user first selects the power-down
between conversions option by using the SLEEP pin and the
power management bits, PMGT1 and PMGT0, in the control
register, (see last section). In this mode the AD7856 automati-
cally enters a full power-down at the end of a conversion, i.e.,
when BUSY goes low. The falling edge of the next CONVST
pulse causes the part to power up. Assuming the external refer-
ence is left powered up, the AD7856 should be ready for normal
operation 5 µs after this falling edge. The rising edge of CONVST
initiates a conversion so the CONVST pulse should be at least
5 µs wide. The part automatically powers down on completion
of the conversion.
5ms 3.5ms
t
CONVERT
POWER-UP
TIME
NORMAL
OPERATION
FULL
POWER-DOWN
POWER-UP
TIME
START CONVERSION ON RISING EDGE
POWER-UP ON FALLING EDGE
CONVST
BUSY
Figure 22. Power-Up Timing When Using
CONVST
Pin
NOTE: Where the software CONVST is used, the part must be
powered up in software with an extra write setting PMGT1 = 0
and PMGT0 = 1 before a conversion is initiated in the next
write. Automatic partial power-down after a calibration is not
possible; the part must be powered down manually. If software
calibrations are to be used when operating in the partial power-
down mode, then three separate writes are required. The first
initiates the type of calibration required, the second write pow-
ers the part down into partial power-down mode, while the third
write powers the part up again before the next calibration com-
mand is issued.
Using the Internal (On-Chip) Reference
As in the case of an external reference, the AD7856 can power-
up from one of two conditions, power-up after the supplies are
connected or power-up from hardware/software power-down.
When using the on-chip reference and powering up when AV
DD
and DV
DD
are first connected, it is recommended that the power-
up calibration mode be disabled as explained above. When using
the on-chip reference, the power-up time is effectively the time
it takes to charge up the external capacitor on the REF
IN
/REF
OUT
pin. This time is given by the equation:
t
UP
= 10 × R × C
where R 150 kand C = external capacitor.
The recommended value of the external capacitor is 100 nF;
this gives a power-up time of approximately 150 ms before a
calibration is initiated and normal operation should commence.
When C
REF
is fully charged, the power-up time from a hardware
or software power-down reduces to 5 µs. This is because an

AD7856KRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V SGL-Supply 8-Ch 14B 285kSPS
Lifecycle:
New from this manufacturer.
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