AD7856
–4–
REV. A
TIMING SPECIFICATIONS
1
(V
DD
= 5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. A Grade: f
CLKIN
= 6 MHz; K Grade: f
CLKIN
= 4 MHz.)
␣ ␣ ␣ Limit at T
MIN
, T
MAX
Parameter A Version K Version Units Description
f
CLKIN
2
500 500 kHz min Master Clock Frequency
6 4 MHz max
f
SCLK
6 4 MHz max
t
1
3
100 100 ns min CONVST Pulsewidth
t
2
50 50 ns max CONVST↓ to BUSY↑ Propagation Delay
t
CONVERT
3.5 5.25 µs max Conversion Time = 20 t
CLKIN
t
3
–0.4 t
SCLK
–0.4 t
SCLK
ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
±0.4 t
SCLK
±0.4 t
SCLK
ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
t
4
4
30 50 ns max Delay from SYNC↓ Until DOUT 3-State Disabled
t
5
4
30 50 ns max Delay from SYNC↓ Until DIN 3-State Disabled
t
6
4
45 75 ns max Data Access Time After SCLK↓
t
7
30 40 ns min Data Setup Time Prior to SCLK↑
t
8
20 20 ns min Data Valid to SCLK Hold Time
t
9
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK High Pulsewidth
t
10
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK Low Pulsewidth
t
11
30 30 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 t
SCLK
30/0.4 t
SCLK
ns min/max (Continuous SCLK)
t
12
5
50 50 ns max Delay from SYNC↑ Until DOUT 3-State Enabled
t
13
90 90 ns max Delay from SCLK↑ to DIN Being Configured as Output
t
14
6
50 50 ns max Delay from SCLK↑ to DIN Being Configured as Input
t
15
2.5 t
CLKIN
2.5 t
CLKIN
ns max CAL↑ to BUSY↑ Delay
t
16
2.5 t
CLKIN
2.5 t
CLKIN
ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence
t
CAL
41.7 62.5 ms typ Full Self-Calibration Time, Master Clock Dependent
(250026 t
CLKIN
)
t
CAL1
37.04 55.5 ms typ Internal DAC Plus System Full-Scale Cal Time, Master
Clock Dependent (222228 t
CLKIN
)
t
CAL2
4.63 6.94 ms typ System Offset Calibration Time, Master Clock Dependent
(27798 t
CLKIN
)
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Table X and timing diagrams for different interface modes and calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
12
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6
t
14
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
14
, quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
Specifications subject to change without notice.
