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NCV7520FPR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
NCV7520
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16
Table 10. DIAGNOSTIC CONFIG 2 REGISTER
R3
A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
0 1 1 X X X X X
X
CH5 CH4 CH3 CH2 CH1
CH0
?
1 = ENABLE DIAGNOSTIC
DEFAULT = ENABLE
OPEN LOAD DIAGNOSTIC ENABLE/DISABLE
Diagnostic Status Registers − Register R4 & R5
Diagnostic status and ENB status information is returned
when R4 or R5 is selected (Table 11) Diagnostic status
information for each channel is 3−bit (ST2:0) priority
encoded (Table 12). Bit D[9] returns the state of the ENB
input e.g. D[9] = 0 when ENB = 0 (enabled). Status is latched
for the currently higher priority fault and is not demoted if
a fault of lower priority occurs. The latched status is not
affected by ENB. Default response after reset is D[8:0] = 1
(“Diagnostic Not Complete”).
When a channel is configured for auto−retry mode, its
status register bits are reset to “Diagnostic Not Complete”
after reading the register (see Figure 18).
When a channel is configured for latch−off mode and no
“SCB” status is present, its register bits are reset to
“Diagnostic Not Complete” after reading the register. If
“SCB” status is present, its register bits are set to “GLO”
after reading the register. This status is maintained until the
channel is un−latched either by successfully executing the
un−latch sequence or by disabling then re−enabling the
device via the ENB input (Figure 18). The “GLO” status
allows the application to detect a latched−off channel in the
event the “SCB” status data is discarded by the controller
due to SPI transmission error.
Table 11. DIAGNOSTIC STATUS REGISTERS
A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
R4
1 0 0 X X X X X X X X X X X X ? SI
1 0 0 0 0 ENB CH2 CH1 CH0 CH2 CH1 CH0 CH2 CH1 CH0 ? SO
R5
1 0 1 X X X X X X X X X X X X ? SI
1 0 1 0 0 ENB CH5 CH4 CH3 CH5 CH4 CH3 CH5 CH4 CH3 ? SO
ST2 ST1 ST0
Table 12. DIAGNOSTIC STATUS ENCODING
ST2 ST1 ST0 STATUS PRIORITY
0 0 0 GLO – GATx LATCHED OFF 0 HIGHEST
0 0 1 SCB − SHORT TO BATTERY 1
0 1 0 SCG − SHORT TO GROUND 2
0 1 1 OLF − OPEN LOAD 3 (Note)
1 0 0 Diagnostic Complete − No Fault 4
1 0 1 No SCB Fault − ON State 5
1 1 0 No SCG/OLF Fault − OFF State 6
1 1 1 Diagnostic Not Complete (DEFAULT) 7 LOWEST
NOTE: OLF status report is suppressed when open load diagnostic is turned off via
Diagnostic Config 2 − register R3
Revision Information − Register R6
Device revision information is returned when R6 is
selected (Table 13). Output bits D[11:8] are hard coded to 0,
bits D[7:6] are encoded with the specific device identifier
(i.e. “00” = 7518, “01” = 7519, “10” = 7520), bits D[5:3] are
hard coded with the die (silicon) revision, and bits D[2:0] are
hard coded with the mask (interconnect) revision. The first
response frame sent after reset is the device revision
information. The revision encoding scheme is shown in
Table 14.
Mask revision may be incremented when an interconnect
revision is made. Die revision is incremented when a silicon
revision is made. Mask revision is reset to “000” when a die
revision is made.
NCV7520
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Table 13. DEVICE REVISION INFORMATION
R6
A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
1 1 0 X X X X X X X X X X X X ? SI
1 1 0 0 0 0 0 1 0 D5 D4 D3 D2 D1 D0 ? SO
DEVICE DIE REV MASK REV
Table 14. DEVICE REVISION ENCODING
D5 D4 D3 D2 D1 D0
DIE REV MASK REV
0 0 0 A 0 0 0 0
0 0 1 B 0 0 1 1
0 1 0 C 0 1 0 2
0 1 1 D 0 1 1 3
1 0 0 E 1 0 0 4
1 0 1 F 1 0 1 5
1 1 0 G 1 1 0 6
1 1 1 H 1 1 1 7
Reserved − Register R7
Register R7 is reserved for factory test use. Data sent to R7
is ignored. In normal operation, R7 is an echo type response
register. In the event of a transmission error, R7 responds
with either a parity or frame error on the next valid frame.
Table 15. TEST MODE REGISTER
R7
A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
1 1 1 X X X X X X X X X X X X ? SI
ECHO INPUT DATA ECHO ? SO
PARITY ERR 0 1 0 1 0 1 0 1 0 1 0 1 0 SO
FRAME ERR 0 1 0 1 0 1 0 1 0 1 0 0 1 SO
Gate Driver Control and Enable
Each GAT
X
output may be turned on by either its
respective parallel IN
X
input or the Gate & Mode Select
register bits R0.G[5:0] via SPI communication. The
device’s RSTB reset and ENB enable inputs can be used to
implement global control functions, such as system reset,
over−voltage or input override by a watchdog controller.
The RSTB input has an internal pull−down resistor and
the ENB input has an internal pull−up resistor. Each parallel
input has an internal pull−down resistor. Parallel input is
recommended when low frequency (≤ 10 kHz) PWM
operation of the outputs is desired. Unused parallel inputs
should be connected to GND.
When RSTB is brought low, all GAT
X
outputs, the timer
clock, the SPI, and the FLTB flag are disabled. All internal
registers are initialized to their default states, status data is
cleared, and the SPI and FLTB are enabled when RSTB goes
high.
ENB disables all GAT
X
outputs and diagnostics, and
resets the auto−retry timer when brought high. The SPI is
enabled, registers remain as programmed, and status data is
not cleared. Latched−off outputs are re−enabled and their
status can be updated when ENB goes low.
The IN
X
input state and the G
X
register bit data are
logically combined with the internal (active low) power−on
reset signal (POR), the RSTB and ENB input states, and the
shorted load state (internal SHRT
X
) to control the
corresponding GAT
X
output such that:
GAT
X
+ POR @ RSTB @ ENB @ SHRT
X
@
ǒ
IN
x
) G
X
Ǔ
(eq. 1)
The GAT
X
state truth table is given in Table 16.
NCV7520
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Table 16. GATE DRIVER TRUTH TABLE
POR
RSTB ENB SHRT
X
IN
X
G
X
GAT
X
0 X X X X X L
1 0 X X X X L
1 1 1 X X X L
1 1 0 1 0 0 L
1 1 0 1 1 X H
1 1 0 1 X 1 H
1 1 0 0 X X →L
1 1 0→1 X X G
X
→L
1 1 1→0 →1 0 G
X
→G
X
1 1→0 X X X →0 →L
Gate Drivers
The non−inverting GAT
X
drivers are symmetrical
resistive switches (350 W typ.) to the VCC2 and VSS
voltages. While the outputs are designed to provide
symmetrical gate drive to an external MOSFET, load current
switching symmetry is dependent on the characteristics of
the external MOSFET and its load. Figure 13 shows the gate
driver block diagram.
DRIVER
VCC2
VSS
FILTER
TIMER
LATCH OFF /
AUTO RE−TRY
DRN
X
GAT
X
FAULT
DETECTION
STX[2:0]
R2.C[4:3]
BLANKING
TIMER
ENCODING
LOGIC
EN
SHRT
X
350
R0.M[ X]
RSTB
ENB
POR
DIAGNOSTIC
PULSE
EN
G
X
IN
X
R1.F|N[X]
R2.C[8:3]
R2.C[11:9]
VSS
R3.D[X,X+6]
Figure 13. Gate Driver Channel
REFRESH TIMER
Blanking and Filter Timers
Blanking timers are used to allow drain feedback to
stabilize after a channel is commanded to change states.
Filter timers are used to suppress glitches while a channel is
in a stable state.
A turn−on blanking timer is started when a channel is
commanded on. Drain feedback is sampled after t
BL(ON)
. A
turn−off blanking timer is started when a channel is
commanded off. Drain feedback is sampled after t
BL(OFF)
.
A filter timer is started when a channel is in a stable state
and a fault detection threshold associated with that state has
been crossed. Drain feedback is sampled after t
FF(ON|OFF)
.
A filter timer may also be started while a blanking timer is
active, so the blanking interval could be extended by the
filter time.
Each channel has independent blanking and filter timers.
The parameters for the t
FF(ON|OFF)
filter timer are the same
for all channels. The turn−on/off blanking time for each
channel can be selected via the Diagnostic Config 1 register
bits R2.C[8:3] (Tables 6 and 8).
If a blanking timer is currently running when the register
is changed, the new value is accepted but will not take effect
until the next activation of the timer.
Blanking timers for all channels are started when both
RSTB goes high and ENB goes low, when RSTB goes high
while ENB is low, when ENB goes low while RSTB is high,
or by POR.
Fault Diagnostics and Behavior
Each channel has independent fault diagnostics and
employs blanking and filter timers to suppress false faults.
An external MOSFET is monitored for fault conditions by
connecting its drain to a channel’s DRN
X
feedback input
through an optional external series resistor.
Shorted load (or short to V
LOAD
) faults can be detected
when a driver is on. Open load or short to GND faults can be
detected when a driver is off.
On−state faults will initiate MOSFET protection
behavior, set the FLTB flag and the respective channel’s
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

NCV7520FPR2G

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Buy NCV7520FPR2G
Manufacturer:
ON Semiconductor
Description:
Gate Drivers AUTOMOTIVE DRIVER
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