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MAX7302ATE+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
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or visit Maxim's website at www.maxim-ic.com.
General Description
The MAX7302 I
2
C-/SMBus™-compatible, serial-interfaced
peripheral features 9 level-translating I/Os, and operates
from a 1.62V to 3.6V power supply. The MAX7302 fea-
tures a port supply V
LA
that allows level-translation on I/O
ports to operate from a separate power supply from 1.62V
to 5.5V. An address select input, AD0, allows up to four
unique slave addresses for the device.
The MAX7302 ports P2–P9 can be configured as inputs,
push-pull outputs, and open-drain outputs. Port P1 can
be configured as a general-purpose input, open-drain
output, or an open-drain INT output. Ports P2–P9 can be
configured as OSCIN and OSCOUT, respectively. Ports
P2–P9 can also be used as configurable logic arrays
(CLAs) to form user-defined logic gates, replacing exter-
nal discrete gates. Outputs are capable of sinking up to
25mA, and sourcing up to 10mA when configured as
push-pull outputs.
The MAX7302 includes an internal oscillator for PWM,
blink, and key debounce, or to cascade multiple
MAX7302s. The external clock can be used to set a spe-
cific PWM and blink timing. The RST input asynchronous-
ly clears the 2-wire interface and terminates a bus lockup
involving the MAX7302.
All ports configured as an output feature a 33-step PWM,
allowing any output to be set from fully off, 1/32 to 31/32
duty cycle, to fully on. All output ports also feature LED
blink control, allowing blink periods of 1/8s, 1/4s, 1/2s, 1s,
2s, 4s, or 8s. Any port can blink during this period with a
1/16 to 15/16 duty cycle.
The MAX7302 is specified over the -40°C to +125°C
temperature range and is available in 16-pin QSOP and
16-pin TQFN (3mm x 3mm) packages.
Applications
Cell Phones
Servers
System I/O Ports
LCD/Keypad Backlights
LED Status Indicators
Features
♦ 1.62V to 5.5V I/O Level-Translation Port Supply (V
LA
)
♦ 1.62V to 3.6V Power Supply
♦ 9 Individually Configurable GPIO Ports
P1 Open-Drain I/O
P2–P9 Push-Pull or Open-Drain I/Os
♦ Individual 33-Step PWM Intensity Control
♦ Blink Controls with 15 Steps on Outputs
♦ 1kHz PWM Period Provides Flicker-Free LED
Intensity Control
♦ 25mA (max) Port Output Sink Current (100mA
max Ground Current)
♦ Inputs Overvoltage Protected Up to 5.5V (V
LA
)
♦ Transition Detection with Optional Interrupt Output
♦ Optional Input Debouncing
♦ I/O Ports Configurable as Logic Gates (CLA)
♦ External RST Input
♦ Oscillator Input and Output Enable Cascading
Multiple Devices
♦ Low 0.75µA (typ) Standby Current
MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-0749; Rev 1; 12/07
Pin Configurations appear at end of data sheet.
EVALUATION KIT
AVAILABLE
SMBus is a trademark of Intel Corp.
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX7302AEE+
-40°C to +125°C
16 QSOP
E16-4
MAX7302ATE+
-40°C to +125°C
16 TQFN-EP*
(3mm x 3mm)
T1633-4
+Denotes lead-free package.
*EP = Exposed paddle.
ADO
μC
SDA
GND
+1.8V
V
DD
V
LA
P2
P3
P4
P5
1.8V OPEN-DRAIN OUTPUT
P6
P7
P8
P9
+4.5V
MAX7302
4.5V PUSH-PULL OUTPUT
4.5V LOGIC INPUT
3.3V LOGIC INPUT
2.5V LOGIC INPUT
SCL
RST
INT
SDA
SCL
RST
P1/INT
Typical Operating Circuit
MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= 1.62V to 3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= 3.3V, V
LA
= 3.3V, T
A
= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
V
DD
..........................................................................-0.3V to +4V
V
LA
, SCL, SDA, AD0, RST, P1..................................-0.3V to +6V
P2–P9 ............................................................-0.3V to V
LA
+ 0.3V
P1–P9 Sink Current ............................................................25mA
P2–P9 Source Current ........................................................10mA
SDA Sink Current ...............................................................10mA
V
DD
Current .......................................................................10mA
V
LA
Current ........................................................................35mA
GND Current ....................................................................100mA
Continuous Power Dissipation (T
A
= +70°C)
16-Pin QSOP (derate 8.3mW/°C over +70°C)..............666mW
16-Pin TQFN (derate 14.7mW/°C over +70°C) ..........1176mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX
Operating Supply Voltage V
DD
1.62 3.60
V
Port Logic Supply Voltage V
LA
1.62 5.50
V
Power-On-Reset Voltage V
POR
V
DD
rising 1.0 1.3 1.6 V
Power-On-Reset Hysteresis
V
PORHYST
10 158 300
I
STB
Internal oscillator disabled;
SCL, SDA, digital inputs at V
DD
or
GND; P1–P9 (as inputs) at V
LA
or
GND
0.75 2
Standby Current (Interface Idle)
I
OSC
Internal oscillator enabled;
SCL, SDA, digital inputs at V
DD
or
GND; P1–P9 (as inputs) at V
LA
or
GND
17 25
µA
S up p l y C ur r ent ( Inter face Runni ng ) I
SUP
f
SCL
= 400kHz;
other d i g i tal i np uts at V
DD
or G N D
31 40 µA
Port Supply Current (V
LA
)I
VLA
Port inputs at V
LA
or GND 0.06 5 µA
Input High Voltage SDA, SCL, AD0, RST V
IH
0.7 x V
DD
V
Input Low Voltage SDA, SCL, AD0, RST V
IL
0.3 x V
DD
V
Input High Voltage P1–P9 V
IHP
Input is V
DD
referred 0.7 x V
DD
V
Input Low Voltage P1–P9 V
ILP
Input is V
DD
referred
0.3 x V
DD
V
Input High Voltage P1–P9 V
IHPA
Input is V
LA
referred 0.7 x V
LA
V
Input Low Voltage P1–P9 V
ILPA
Input is V
LA
referred
0.3 x V
LA
V
Inp ut Leakag e C ur r ent S D A, S C L, AD 0, RST
I
IH
, I
IL
V
DD
or GND -1 +1 µA
Input Leakage Current P1–P9
I
IHP
, I
ILP
V
LA
or GND -2 +2 µA
Input Capacitance SDA, SCL, AD0,
P1–P9, RST
8pF
V
DD
= 1.62V, I
SINK
= 3mA 0.05
0.11
V
DD
= 2.5V, I
SINK
= 16mA 0.19
0.31
Output Low Voltage P1–P9 V
OL
V
DD
= 3.3V, I
SINK
= 20mA 0.19
0.31
V
V
LA
= 1.62V, I
SOURCE
= 0.5mA
1.55
1.58
V
LA
≥ 2.5V, I
SOURCE
= 5mA
V
LA
- 0.
4
2.32Output High Voltage P2–P9 V
OH
V
LA
≥ 3.3V, I
SOURCE
= 10mA
V
LA
- 0.6
3.1
V
Output Low Voltage SDA
V
OLSDA
I
SINK
= 6mA 0.3 V
MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
_______________________________________________________________________________________ 3
PORT, INTERRUPT (INT), AND RESET (RST) TIMING CHARACTERISTICS
(V
DD
= 1.62V to 3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= 3.3V, V
LA
= 3.3V, T
A
= +25°C.) (Note 1)
(Figures 10, 15, 16 and 17)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
CLK
= internal oscillator 32 kHz
Oscillator Frequency f
CLK
f
C LK
= OS C IN exter nal i np ut
1 MHz
Port Output Data Valid High Time t
PPVH
C
L
≤ 100pF 4 µs
Port Output Data Valid Low Time (Note 6) t
PPVL
C
L
≤ 100pF (Note 2)
1/f
CLK
s
Port Input Setup Time t
PSU
C
L
= 100pF 0 µs
Port Input Hold Time t
PH
C
L
= 100pF 4 µs
CLA Rise Time P5, P9 as Push-Pull Outputs 17
CLA Fall Time P5, P9 as Push-Pull Outputs
t
RFCLA
C
L
= 100pF, V
LA
≥ 2.7V
14
ns
CLA Propagation Delay P2, P3, or P4 to P5; P6, P7,
or P8 to P9
t
PDCLA
C
L
= 100pF, V
LA
≥ 2.7V 28 50 ns
INT Input Data Valid Time t
IV
C
L
= 100pF 4 µs
INT Reset Delay Time from Acknowledge t
IR
C
L
= 100pF 4 µs
RST Rising to START Condition Setup Time t
RST
900
ns
RST Pulse Width t
W
500
ns
SERIAL INTERFACE TIMING CHARACTERISTICS
(V
DD
= 1.62V to 3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= 3.3V, V
LA
= 3.3V, T
A
= +25°C.) (Note 1)
(Figure 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency f
SCL
400
kHz
Bus Timeout
t
TIMEOUT
31 ms
Bus Fr ee Tim e Betw een a S TOP and a S TART C ond i ti on
t
BUF
1.3
µs
Hold Time, (Repeated) START Condition
t
HD
,
STA
0.6
µs
Repeated START Condition Setup Time
t
SU
,
STA
0.6
µs
STOP Condition Setup Time
t
SU
,
STO
0.6
µs
Data Hold Time
t
HD
,
DAT
(Note 3)
0.9
µs
Data Setup Time
t
SU
,
DAT
100
ns
SCL Clock Low Period t
LOW
1.3
µs
SCL Clock High Period t
HIGH
0.7
µs
Rise Time of Both SDA and SCL Signals, Receiving
t
R
(Notes 2, 4)
20 + 0.1C
b
300
ns
Fall Time of Both SDA and SCL Signals, Receiving
t
F
(Notes 2, 4)
20 + 0.1C
b
300
ns
Fall Time of SDA Transmitting t
F.TX
(Note 4)
20 + 0.1C
b
250
ns
Pulse Width of Spike Suppressed t
SP
(Note 5) 50 ns
C ap aci ti ve Load for E ach Bus Li ne C
b
(Note 2)
400
pF
Note 1: All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge the
undefined region of SCL’s falling edge.
Note 4: C
b
= total capacitance of one bus line in pF. t
R
and t
F
are measured between 0.3 x V
DD
and 0.7 x V
DD
.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 6: A startup time is required for the internal oscilator to start if it is not running already.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

MAX7302ATE+

Mfr. #:
Buy MAX7302ATE+
Manufacturer:
Maxim Integrated
Description:
Interface - I/O Expanders 9-Port Level-Trans GPIO & LED Driver
Lifecycle:
New from this manufacturer.
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