MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
10 ______________________________________________________________________________________
Slave Address
The MAX7302 is set to one of four I
2
C slave addresses,
using the address input AD0 (see Table 5) and is
accessed over an I
2
C or SMBus serial interface up to
400kHz. The MAX7302 slave address is determined on
each I
2
C transmission, regardless of whether or not the
transmission is actually addressing the device. The
MAX7302 distinguishes whether address input AD0 is
connected to SDA, SCL, V
DD
, or GND during the trans-
mission. Therefore, the MAX7302 slave address can be
configured dynamically in an application without tog-
gling the device supply.
I/O Port Registers
The port I/O registers set the I/O ports, one register per
port (see Tables 6 and 7). Ports can be independently
configured as inputs or outputs (D7), push-pull or open
drain (D6). Port P1 can only be configured as an input or
an open-drain output. The push-pull bit (D6) setting for
the port I/O register P1 is ignored.
I/O Input Port
Configure a port as an input by writing a logic-high to
the MSB (bit D7) of the port I/O register (see Table 6).
See Figure 1 for input port structure. To obtain the logic
level of the port input, read the port I/O register bit, D0.
This readback value is the instantaneous logic level at
the time of the read request if debounce is disabled for
the port (port I/O register bit D2 = 0), or the debounced
result if debounce is enabled for the port (port I/O reg-
ister bit D2 = 1).
I/O Output Port
Configure a port as an output by writing a logic-low to the
MSB (bit D7) of the port I/O register. See Figures 2 and 3
for output port structure. The device reads back the logic
level, PWM, or the blink setting of the port (see Table 7).
The MAX7302 monitors the logic level of ports configured
as CLA outputs (see the Configurable Logic Array (CLA)
section).
Port Supplies and Level Translation
The port supply, V
LA
, provides the logic supplies to all
push-pull I/O ports. Ports P2–P9 can be configured as
push-pull I/O ports (see Figure 3). V
LA
powers the logic-
high port output voltage sourcing the logic-high port load
current. V
LA
provides level translation capability for the
outputs and operates over a 1.62V to 5.5V voltage inde-
pendent of the MAX7302 power-supply voltage, V
DD
.
Each port set as an input can be configured to switch
midrail of either the V
DD
or the V
LA
port supplies.
Whenever the port supply reference is changed from V
DD
to V
LA
, or vice versa, read the port register to clear any
transition flag on the port.
FUNCTION
D7 Port I/O set bit 1 Sets the I/O port as an input.
0 Refers the input to the V
LA
supply voltage.
D6
Port supply
reference
1 Refers the input to the V
DD
supply voltage.
0 Disables the transition interrupt.
D5
Transition interrupt
enable
1 Enables the transition interrupt.
D4, D3 Reserved bits 0 Do not write to these registers.
0 Disables debouncing of the input port.
D2 Debounce
1 Enables debouncing of the input port.
0 No transition has occurred since the last port read.
D1
Port transition state
(read only)
1 A transition has occurred since the last port read.
0 Port input is logic-low.
D0
Port status
(read only)
1 Port input is logic-high.
