MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
22 ______________________________________________________________________________________
Serial Interface
Serial Addressing
The MAX7302 operates as a slave that sends and
receives data through an I
2
C-compatible, 2-wire inter-
face. The interface uses a serial-data line (SDA) and a
serial-clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7302 and generates the SCL clock that
synchronizes the data transfer (see Figure 10).
The MAX7302 SDA line operates as both an input and
an open-drain output. A 4.7kΩ (typ) pullup resistor is
required on SDA. The MAX7302 SCL line operates only
as an input. A 4.7kΩ (typ) pullup resistor is required on
SCL if there are multiple masters on the 2-wire inter-
face, or if the master in a single-master system has an
open-drain SCL output.
Each transmission consists of a START condition (see
Figure 11) sent by a master, followed by the MAX7302
7-bit slave address plus R/W bit, a register address byte,
one or more data bytes, and finally a STOP condition
(see Figure 11).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (see Figure 11).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(see Figure 12).
SCL
SDA
t
R
t
F
t
BUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
t
SU,STO
t
HD,STA
t
SU,STA
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
t
HD,STA
RESET
t
WL(RST)
Figure 10. 2-Wire Serial Interface Timing Details
SDA
SCL
START
CONDITION
STOP
CONDITION
SP
Figure 11. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 12. Bit Transfer
MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
______________________________________________________________________________________ 23
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data (see
Figure 13). Thus, each effectively transferred byte
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX7302, the MAX7302
generates the acknowledge bit because the MAX7302
is the recipient. When the MAX7302 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
The Slave Address
The MAX7302 has a 7-bit long slave address (Figure
14). The 8th bit following the 7-bit slave address is the
R/W bit. Set R/W bit low for a write command and high
for a read command.
The first 5 bits of the MAX7302 slave address (A6–A2)
are always 1, 0, 0, 1, and 1. Slave address bit A1, A0 is
selected by the address input AD0. AD0 can be con-
nected to GND, V
DD
, SDA, or SCL. The MAX7302 has
four possible slave addresses (see Table 5), and there-
fore, a maximum of four MAX7302 devices can be con-
trolled independently from the same interface.
Message Format for Writing to the MAX7302
A write to the MAX7302 comprises the transmission of the
MAX7302’s slave address with the R/W bit set to zero, fol-
lowed by at least 1 byte of information (see Figure 16).
The first byte of information is the command byte. The
command byte determines which register of the
MAX7302 is to be written to by the next byte, if received.
If a STOP condition is detected after the command byte is
received, the MAX7302 takes no further action beyond
storing the command byte (see Figure 15).
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX7302 selected by the command byte (see Figure
16). If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored in
subsequent MAX7302 internal registers because the
command byte address autoincrements (see Table 3).
Message Format for Reading
The MAX7302 is read using the MAX7302’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read using the same rules as for a
write. Thus, a read is initiated by first configuring the
MAX7302’s command byte by performing a write
(Figure 15). The master can now read n consecutive
bytes from the MAX7302 with the first data byte being
read from the register addressed by the initialized com-
mand byte (see Figure 17). When performing read-
after-write verification, remember to reset the command
byte’s address because the stored command byte
address has been autoincremented after the write.
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGE
START
CONDITION
SDA BY
RECEIVER
12 89
S
Figure 13. Acknowledge
SDA
SCL
0
R/W
MSB LSB
ACK
A1
1
0A0
11
Figure 14. Slave Address
SAA
P
0SLAVE ADDRESS REGISTER ADDRESS
ACKNOWLEDGE FROM MAX7302
D15 D14 D13 D12 D11 D10 D9 D8
ACKNOWLEDGE FROM MAX7302
R/W
Figure 15. Register Address Received
MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
24 ______________________________________________________________________________________
Operation with Multiple Masters
If the MAX7302 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7302
should use a repeated start between the write that sets
the MAX7302’s address pointer, and the read(s) that
takes the data from the location(s). This is because it is
possible for master 2 to take over the bus after master
1 has set up the MAX7302’s address pointer, but
before master 1 has read the data. If master 2 subse-
quently changes the MAX7302’s address pointer, then
master 1’s delayed read can be from an unexpected
location.
Bus Timeout
Clear device configuration register 0x27 bit D7 to
enable the bus timeout function (see Table 4), or set it
to disable the bus timeout function. Enabling the time-
out feature resets the MAX7302 serial-bus interface
when SCL stops either high or low during a read or
write. If either SCL or SDA is low for more than nominal-
ly 31ms after the start of a valid serial transfer, the inter-
face resets itself and sets up SDA as an input. The
MAX7302 then waits for another START condition.
1 2 3 4 5 6 7 8 9
S 1 0 0 1 1 A1 A0 0 A 0 0 0 0 0 1 0 0 A A P
t
PPV
SLAVE ADDRESS COMMAND BYTE
MSB DATA LSB
SCL
SDA
P9 TO P1
START CONDITION
R/W
DATA VALID
A
ACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE
STOP
WRITE TO OUTPUT PORTS REGISTERS
(P4)
Figure 16. Write to Output Port Registers
1 2 3 4 5
6 7 8 9
S 1 0 0 1 1 A1 A0 1 A A
SCL
SDA
P9 TO P1
DATA1
t
PH
t
PSU
DATA2 DATA3 DATA4
NA P
NO ACKNOWLEDGE
START CONDITION
STOP
READ FROM INPUT PORTS REGISTERS
R/W
ACKNOWLEDGE FROM SLAVE
MSB DATA1 LSB MSB DATA4 LSB
ACKNOWLEDGE FROM MASTER
Figure 17. Read from Input Port Registers
1 2 3 4 5 6 7 8 9
S 1 0 0 1 1 A1 A0 1 A AMSB DATA2 LSB
SCL
SDA
P9 TO P1
DATA1
t
IV
t
IV
t
IR
t
IR
DATA2
NA P
START CONDITION
STOP
DATA3
INT
INTERRUPT VALID/RESET
R/W
ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM MASTER
MSB DATA3 LSB
NO ACKNOWLEDGE
Figure 18. Interrupt and Reset Timing

MAX7302ATE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Interface - I/O Expanders 9-Port Level-Trans GPIO & LED Driver
Lifecycle:
New from this manufacturer.
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