LC75836WH-E Datasheet LC75836WH-E, LC75836W-E, LC75836W-TBM-E | P13-P15

LC75836W

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13

Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)

Control data

Frame frequency fo [Hz]

FC0 FC1 FC2

1 1 0 fosc/768,f

CK

/768

1 1 1 fosc/576,f

CK

/576

0 0 0 fosc/384,f

CK

/384

0 0 1 fosc/288,f

CK

/288

0 1 0 fosc/192,f

CK

/192

V

DD

1

V

DD

2

fo[Hz]

V

DD

COM3

COM2

COM1

COM4

LCD driver output when all LCD segments corresponding

to COM1, COM2, COM3, and COM4 are on.

LCD driver output when LCD segments

corresponding to COM2, and COM4 are on.

LCD driver output when only LCD segments

corresponding to COM4 are on.

LCD driver output when LCD segments corresponding

to COM1, COM2, and COM3 are on.

LCD driver output when LCD segments

corresponding to COM2 and COM3 are on.

LCD driver output when LCD segments

corresponding to COM1 and COM3 are on.

LCD driver output when only LCD segments

corresponding to COM3 are on.

LCD driver output when LCD segments

corresponding to COM1 and COM2 are on.

LCD driver output when only LCD segments

corresponding to COM2 are on.

LCD driver output when only LCD segments

corresponding to COM1 are on.

LCD driver output when all LCD segments corresponding to

COM1, COM2, COM3, and COM4 are off.

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

VD

D

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

V

DD

1

V

DD

2

V

DD

0V

LC75836W

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14

Display Control and the

INH

Since the LSI internal data (the display data D1 to D140 and the control data) is undefined when power is first applied,

applications should set the INH

pin low at the same time as power is applied to turn off the display. (This sets the S1/P1

to S4/P4, S5 to S35, and COM1 to COM4 pins to the V

SS

level.) and during this period send serial data from the

controller. The controller should then set the INH

pin high after the data transfer has completed. This procedure

prevents meaningless displays at power on.

(See Figure 5.)

Figure 5



Notes: t1>0

tc10s min

Display data and control data dtratransterred

V

DD

t1

D1 to D36,

Internal data FC0 to FC2, P0 to P2,

OC, SC, BU

Internal data (D37 to D72)

Internal data (D73 to D108)

Undefined

CE

INH

Undefined

Undefined Defined

Defined

Undefined

V

IL

1

tc

V

IL

1

Internal data (D109 to D140)

  



 



LC75836W

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15

Notes on Controller Transfer of Display Data

Since the LC75836W transfer the display data (D1 to D140) in four separate transfer operations, we recommend that

applications make a point of completing all four data transfers within a period of less than 30ms to prevent

observable degradation of display quality.

OSC Pin Peripheral Circuit

(1) RC oscillator operating mode (control data OC = 0)

An external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and GND if

RC oscillator operating mode is selected.

(2) External clock operating mode (control data OC = 1)

When the external clock operating mode is selected, insert a current protection resistor Rg (4.7 to 47 k) between

the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to

the allowable current value at the external clock output pin. Also make sure that the waveform of the external

clock is not heavily distorted.

Note: Allowable current value at external clock output pin >

V

DD

Rg

OSC External clock output pin

Rg

External oscillator

OSC

Cosc Rosc

LC75836WH-E

LC75836WH-E

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