10
FN2951.4
October 1, 2015
Timing Waveforms
FIGURE 8.
FIGURE 9. CLOCK TIMING
FIGURE 10. OUTPUT WAVEFORM
DATA SYNC
BIT PERIOD BIT PERIOD BIT PERIOD
t
2
COMMAND SYNC
t
2
t
3
t
3
t
2
t
2
t
4
ONEONE ZERO
T
1
t
1
t
1
t
3
t
3
t
1
t
1
t
1
t
3
t
3
t
3
t
3
t
1
t
4
t
5
t
5
t
2
t
2
COMMAND SYNC
t
2
t
2
t
4
t
5
t
5
t
4
t
4
ZERO ONE ONEONE
DATA SYNC
BOI
BZI
BOI
BZI
BOI
BZI
UDI
UDI
UDI
t
3
NOTE: UDI = 0, FOR NEXT DIAGRAMS
NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS
t
C
t
CH
t
r
t
CL
t
f
10%
90%
t
r
t
f
1.0V
3.5V
HD-6409HD-6409
11
FN2951.4
October 1, 2015
FIGURE 11. ENCODER TIMING
FIGURE 12. ENCODER TIMING FIGURE 13. ENCODER TIMING
NOTE: Manchester Data-In is not synchronous with Decoder Clock.
Decoder Clock is synchronous with decoded NRZ out of SDO.
FIGURE 14. DECODER TIMING
FIGURE 15. DECODER TIMING FIGURE 16. DECODER TIMING
Timing Waveforms (Continued)
ECLK
SD/CDS
BZO
BOO
t
CE1
t
CE2
t
CE3
t
CE5
t
CE4
CTS
BZO
BOO
ECLK
t
CE6
CTS
BZO
BOO
ECLK
t
CE7
DCLK
UDI
SDO
NVM
MANCHESTER
LOGIC-1
MANCHESTER
LOGIC-0
MANCHESTER
LOGIC-0
MANCHESTER
LOGIC-1
t
CD2
t
CD5
t
CD2
t
CD1
NRZ
LOGIC-1
RST
DCLK, SDO,
NVM
50%
50%
t
CD3
RST
DCLK
50%
t
CD4
HD-6409HD-6409
12
FN2951.4
October 1, 2015
Test Load Circuit
FIGURE 17. REPEATER TIMING
Timing Waveforms (Continued)
UDI
ECLK
BZO
SDO
NVM
MANCHESTER ‘1’
t
R2
t
R3
t
R3
t
R2
t
R1
MANCHESTER ‘0’ MANCHESTER ‘0’ MANCHESTER ‘1’
MANCHESTER ‘1’ MANCHESTER ‘0’ MANCHESTER ‘0’
FIGURE 18. TEST LOAD CIRCUIT
DUT
C
L
(NOTE)
NOTE: INCLUDES STRAY AND JIG
CAPACITANCE
HD-6409HD-6409

HD9P6409-9Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Encoders, Decoders, Multiplexers & Demultiplexers W/ANNEAL ENC/DEC 1MHZ 20 -40+85C
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet