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ADV7604BBCZ-5P

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet ADV7604
Rev. D | Page 9 of 20
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD to GND 2.2 V
DVDD to GND 2.2 V
PVDD to GND 2.2 V
DVDDIO to GND 4.0 V
CVDD to GND 2.2 V
TVDD to GND
4.0 V
Digital Inputs Voltage to GND
GND − 0.3 V to
DVDDIO + 0.3 V
5 V Tolerant Digital Inputs to GND
1
5.3 V
Digital Output Voltage to GND
GND − 0.3 V to
DVDDIO + 0.3 V
Analog Inputs to GND
GND − 0.3 V to
AVDD + 0.3 V
XTAL Pins
−0.3 V to PVDD
to 0.3 V
Maximum Junction Temperature (T
J
MAX
) 125°C
Storage Temperature
150°C
Infrared Reflow Soldering (20 sec)
260°C
1
The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1, HS_IN2,
VS_IN1, VS_IN2, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL,
DDCC_SDA, DDCD_SCL, DDCD_SDA, RXA_5V, RXB_5V, RXC_5V, RXD_5V,
SHARED_EDID,
PWRDN
, EP_MISO.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the ADV7604, the
user is advised to turn off unused sections of the part.
Due to printed circuit board metal variation and, thus, variation
in PCB heat conductivity, the value of θ
JA
may differ for various
PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this eliminates the variance associated with the θ
JA
value.
The maximum junction temperature (T
J MAX
) of 125°C must not
be exceeded. The following equation calculates the junction
temperature using the measured package surface temperature
and applies only when no heat sink is used on DUT:
T
J
= T
S
+ (Ψ
JT
× W
TOTA L
)
where:
T
S
= the package surface temperature (°C).
Ψ
JT
= 0.3°C/W for a 260-ball CSP_BGA.
W
TOTA L
= ((PVDD × I
PVDD
) + (0.05 × TVDD × I
TVDD
) + (CVDD ×
I
CVDD
) + (AVDD × I
AV DD
) + (DVDD × I
DVDD
) + (DVDDIO ×
I
DVDDIO
)).
Note that for W
T O TA L
, 5% of TVDD power is dissipated on the
part itself.
ESD CAUTION
ADV7604 Data Sheet
Rev. D | Page 10 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
07971-005
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DGND RXD_2– RXD_1– RXD_0– RXD_C– DGND RXC_2– RXC_1– RXC_0– RXC_C– TVDD RXB_2– RXB_1– RXB_0– RXB_C– TVDD TVDD DGND
RXD_5V RXD_2+ RXD_1+ RXD_0+ RXD_C+ TVDD RXC_2+ RXC_1+ RXC_0+ RXC_C+ TVDD RXB_2+ RXB_1+ RXB_0+ RXB_C+ TVDD RXA_2+ RXA_2–
TVDD TVDD CVDD DGND TVDD TVDD DGND DGND DGND TVDD TVDD DGND DGND DGND
DGND
RXA_1+ RXA_1–
RXC_5V RXB_5V RXA_5V
DDCD_
SDA
DDCD_
SCL
DDCC_
SDA
DDCC_
SCL
CVDD DGND RTERM CVDD
DDCB_
SDA
DDCB_
SCL
DDCA_
SCL
DDCA_
SDA
TVDD
RXA_0+ RXA_0–
DE CEC NC NC
NC NC
DGND DGND RXA_C+ RXA_C–
HS
VS_
FIELD
EP_MISO EP_MOSI
DGND
CVDD
TVDD DGND
P1 P0 EP_CS EP_SCK
DGND DGND DGND DGND PVDD PVDD
TEST1 TEST2
P3 P2
RAW_
VSYNC
RAW_
SYNC
DGND DGND DGND DGND AGND AGND
XTALP AVDD REFN REFP
DGND DGND
MCLK
OUT
SPDIF/
DSD0A/
DST
DVDD DGND DGND DGND AGND AGND XTALN
AVDD
AGND AGND
P4 P5
LRCLK/
DSD2B/
DST_FF
SCLK/
DST_CLK
DVDD DVDD DGND DGND AGND AVDD AVDD
AVDD
AIN11 AIN12
P6 P7
I2S3/
DSD2A/
HBR3
I2S2/
DSD1B/
HBR2
DVDD DVDD DGND DGND AGND AVDD
TRI8/VS_
IN2
TRI7/HS_
IN2
SYNC4 AIN10
P8 DGND DGND DGND DVDD DVDD DGND DGND AGND AVDD TRI5 TRI6 AGND AGND
P9 DVDDIO DVDDIO DVDDIO TRI3 TRI4 AIN8 AIN9
P10 P11
I2S0/
DSD0B/
HBR0
I2S1/
DSD1A/
HBR1
AVDD AVDD SYNC3 AIN7
P12 P13 DGND DGND SCL DVDDIO INT1 CLAMPIN DVDDIO DGND FB_OUT
SHARED_
EDID
HS_IN1 AGND
Y_MUX_
OUT
TRI2 AGND AGND
P14 P15 DGND DGND P25 DVDDIO SDA
SYNC_
OUT/INT2
DVDDIO DGND RESET AVLINK VS_IN1 AGND TRI1
SYNC2
AIN5 AIN6
P16 P17 P19 P21 P23 DGND P26 DCLKIN P28 DGND P31 P33 P35 AGND SYNC1
AVDD
AVDD AIN4
DGND P18 P20 P22 P24 DGND P27 LLC P29 DGND P30 P32 P34 AGND AIN1 AIN2 AIN3 AGND
PWRDN
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type
Description
A1 DGND Ground Ground.
A2 RXD_2− HDMI input Digital Input Channel 2 Complement of Port D in the HDMI Interface.
A3 RXD_1− HDMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface.
A4 RXD_0− HDMI input Digital Input Channel 0 Complement of Port D in the HDMI Interface.
A5 RXD_C− HDMI input Digital Input Clock Complement of Port D in the HDMI Interface.
A6 DGND Ground Ground.
A7 RXC_2− HDMI input Digital Input Channel 2 Complement of Port C in the HDMI Interface.
A8 RXC_1− HDMI input Digital Input Channel 1 Complement of Port C in the HDMI Interface.
A9 RXC_0− HDMI input Digital Input Channel 0 Complement of Port C in the HDMI Interface.
A10 RXC_C− HDMI input Digital Input Clock Complement of Port C in the HDMI Interface.
A11 TVDD Power Terminator Supply Voltage (3.3 V).
A12 RXB_2− HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface.
A13 RXB_1− HDMI input Digital Input Channel 1 Complement of Port D in the HDMI Interface.
A14 RXB_0− HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface.
A15 RXB_C− HDMI input Digital Input Clock Complement of Port B in the HDMI Interface.
Data Sheet ADV7604
Rev. D | Page 11 of 20
Pin No. Mnemonic Type
Description
A16 TVDD Power Terminator Supply Voltage (3.3 V).
A17 TVDD Power Terminator Supply Voltage (3.3 V).
A18 DGND Ground Ground.
B1 RXD_5V HDMI input 5 V Detect Pin for Port D in the HDMI Interface.
B2 RXD_2+ HDMI input Digital Input Channel 2 True of Port D in the HDMI Interface.
B3 RXD_1+ HDMI input Digital Input Channel 1 True of Port D in the HDMI Interface.
B4 RXD_0+ HDMI input Digital Input Channel 0 True of Port D in the HDMI Interface.
B5 RXD_C+ HDMI input Digital Input Clock True of Port D in the HDMI Interface.
B6 TVDD Power Terminator Supply Voltage (3.3 V).
B7 RXC_2+ HDMI input Digital Input Channel 2 True of Port C in the HDMI Interface.
B8 RXC_1+ HDMI input Digital Input Channel 1 True of Port C in the HDMI Interface.
B9 RXC_0+ HDMI input Digital Input Channel 0 True of Port C in the HDMI Interface.
B10 RXC_C+ HDMI input Digital Input Clock True of Port C in the HDMI Interface.
B11 TVDD Power Terminator Supply Voltage (3.3 V).
B12 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface.
B13 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface.
B14 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface.
B15 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface.
B16 TVDD Power Terminator Supply Voltage (3.3 V).
B17 RXA_2+ HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface.
B18 RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface.
C1
PWRDN
Input
Active Low System Power Detect. If low, EDID can be powered from 5 V signal of
HDMI port when connected to active equipment.
C2 TVDD Power Terminator Supply Voltage (3.3 V ).
C3 TVDD Power Terminator Supply Voltage (3.3 V ).
C4 CVDD Power Comparator Supply Voltage (1.8 V).
C5 DGND Ground Ground.
C6 TVDD Power Terminator Supply Voltage (3.3 V).
C7 TVDD Power Terminator Supply Voltage (3.3 V ).
C8 DGND Ground Ground.
C9 DGND Ground Ground.
C10 DGND Ground Ground.
C11 TVDD Power Terminator Supply Voltage (3.3 V).
C12 TVDD Power Terminator Supply Voltage (3.3 V).
C13 DGND Ground Ground.
C14 DGND Ground Ground.
C15 DGND Ground Ground.
C16 DGND Ground Ground.
C17 RXA_1+ HDMI input Digital Input Channel 1 Complement of Port A in the HDMI interface.
C18 RXA_1− HDMI input Digital Input Channel 1 Complement of Port A in the HDMI interface.
D1 RXC_5V HDMI input 5 V Detect Pin for Port C in the HDMI Interface.
D2 RXB_5V HDMI input 5 V Detect Pin for Port B in the HDMI Interface.
D3 RXA_5V HDMI input 5 V Detect Pin for Port A in the HDMI Interface.
D4 DDCD_SDA HDMI input HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input that is 5 V tolerant.
D5 DDCD_SCL HDMI input HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.
D6 DDCC_SDA HDMI input HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input that is 5 V tolerant.
D7 DDCC_SCL HDMI input HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.
D8 CVDD Power Comparator Supply Voltage (1.8 V).
D9 DGND Ground Ground.
D10 RTERM
Miscellaneous
analog
Terminal Resistance. This pin sets internal termination resistance. Use a 500 Ω
resistor between this pin and GND.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADV7604BBCZ-5P

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