Data Sheet ADV7604
Rev. D | Page 17 of 20
THEORY OF OPERATION
ANALOG FRONT END
The ADV7604 analog front end comprises three 170 MHz, 12-bit
ADCs that digitize the analog video signal before applying it to
the CP, enabling true 12-bit video decoding. The analog front
end uses differential channels to each ADC to ensure high
performance in a mixed-signal application.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7604 without
the requirement of an external mux.
Three voltage clamp control loops ensure that any dc offsets are
removed from the video signal. The voltage clamps are positioned
in front of each ADC to ensure that the video signal remains within
the range of the converter. Fine clamping of the video signals is
performed downstream by digital fine clamping in the CP.
For component 525i, 625i, 525p, and 625p sources, 2× over-
sampling is performed. All other video standards are 1×
oversampled. Oversampling the video signals reduces the
cost and complexity of external antialiasing filters with the
benefit of an increased signal-to-noise ratio (SNR).
HDMI RECEIVER
The HDMI receiver on the ADV7604 incorporates active
equalization of the HDMI data signals. This equalization
compensates for the high frequency losses inherent in HDMI and
DVI cabling, especially at longer lengths and higher frequencies.
The equalization is programmable. It is capable of equalizing
for cable lengths up to 30 meters to achieve robust receiver
performance at even the highest HDMI data rates. The HDMI
receiver supports all HDTV formats up to 1080p and all display
resolutions up to UXGA (1600 × 1200 at 60 Hz). The receiver
contains a programmable data island packet interrupt generator.
With the inclusion of HDCP, displays can receive encrypted video
content. The HDM I interface of the ADV7604 allows for authen-
tication of a video receiver, decryption of encoded data at the
receiver, and renewability of that authentication during trans-
mission as specified by the HDCP 1.3 protocol.
The HDMI receiver offers advanced audio functionality. It supports
multichannel I
2
S audio for up to eight channels. It also supports
a 6-DSD channel interface with each channel carrying an over-
sampled 1-bit representation of the audio signal as delivered on
a super audio CD (SACD). It incorporates a DST interface that
outputs audio data decoded from DST audio packets. The
ADV7604 can also receive HBR audio packet streams and
outputs them through the HBR interface in an SPDIF format
conforming to the IEC60958 standard. It supports multichannel
I
2
S audio for up to eight channels. The receiver also contains an
audio mute controller that can detect a variety of conditions
that may result in audible extraneous noise in the audio output.
On detection of these conditions, the audio data can be ramped
to prevent audio clicks or pops.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many
other standards.
The CP section of the ADV7604 contains an AGC block. In
cases where no embedded synchronization is present, the
video gain can be set manually. The AGC section is followed
by a digital clamp circuit that ensures that the video signal is
clamped to the correct blanking level. Automatic adjustments
within the CP include gain (contrast) and offset (brightness);
manual adjustment controls are also supported.
A fully programmable any-to-any 3 × 3 color space conversion
(CSC) matrix is placed between the analog front end and the
CP section. This enables YPrPb-to-RGB and RGB-to-YC r Cb
conversions. Many other standards of color space can be
implemented using the color space converter.
The CP section contains circuitry to enable the detection of
Macrovision® encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of CGMS data is performed by the CP section
of the ADV7604 for interlaced, progressive, and high definition
scanning rates. The data extracted can be read back over the I
2
C
interface.
CP PIXEL DATA OUTPUT MODES
The output section of the CP is highly flexible. It can be
configured in an SDR mode with one data packet per clock
cycle or in a DDR mode where data is presented on the rising
and falling edge of the clock. In SDR mode, a 16-/20-/24-bit
4:2:2 or 24-/30-/36-bit 4:4:4 output is possible. In these modes,
the HS, VS/FIELD, and DE/FIELD (where applicable) timing
reference signals are provided. In DDR mode, the ADV7604
can be configured in an 8-/10-/12-bit 4:2:2 YCrCb or 12-bit 4:4:4
RGB/YCrCb pixel output interface with corresponding timing
signals.
