ADV7604 Data Sheet
Rev. D | Page 4 of 20
SPECIFICATIONS
AVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, CVDD = 1.8 V ± 5%,
T
MIN
to T
MAX
= −40°C to +70°C.
ANALOG, DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
External Clamp Capacitor 100 nF
Input Impedance Clamps switched off 10 MΩ
ADC Midscale (CML) 0.89 V
ADC Full-Scale Level CML + 0.550 V
ADC Zero-Scale Level CML − 0.550 V
ADC Dynamic Range 1.1 V
Clamp Level (When Locked) Component input (Y signal) CML − 0.130 V
Component input (Pr signal) CML V
Component input (Pb signal) CML V
PC RGB input (R, G, B) CML − 0.130 V
DIGITAL INPUTS
Input High Voltage (V
IH
) 2 V
Input Low Voltage (V
IL
)
Input Current (I
IN
)
RESET
−60 +60 µA
Other digital inputs −10 +10 µA
Input Capacitance (C
IN
) 10 pF
DIGITAL INPUTS (5 V TOLERANT)
1
Input High Voltage (V
IH
)
2.6 V
Input Low Voltage (V
IL
)
0.8 V
Input Current (I
IN
) SHARED_EDID pin −150 +60 µA
Other 5 V digital inputs −82 +82 µA
DIGITAL OUTPUTS
Output High Voltage (V
OH
)
2.4 V
Output Low Voltage (V
OL
) 0.4 V
High Impedance Leakage Current (I
LEAK
) 10 µA
Output Capacitance (C
OUT
) 20 pF
HDMI
TMDS Differential Pin Capacitance 0.3 pF
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew for TMDS
Clock Rates up to 222.75 MHz
0.4 T
BIT
ps
Intrapair (+ to −) Differential Input Skew for TMDS
Clock Rates Above 222.75 MHz
0.15 T
BIT
+ 112
ps
Channel-to-Channel Differential Input Skew
PIXEL
1.78
ns
TM
25 225 MHz
Input Clock Jitter Tolerance 0.5 0.25 T
BIT
T
BIT
1
The following pins are 5 V tolerant: HS_IN1, HS_IN2, VS_IN1, VS_IN2, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA,
RXA_5V, RXB_5V, RXC_5V, RXD_5V, SHARED_EDID,
PWRDN
, EP_MISO.
