ICS9LRS4103
IDT
®
PC MAIN CLOCK 1520A—03/16/10
32-pin CK505 for Intel Systems
1
DATASHEET
Pin Configuration
Recommended Application:
CK505 clock, 32-pin for 5 series Intel chipsets
Output Features:
1 - CPU differential low power push-pull pairs
1 - SRC differential low power push-pull pairs
1 - Selectable 120MHz CK_SSC_Disp or 100 MHz SRC low
power push-pull pair
1 - SATA/SRC selectable differential low power push-pull pair
1 - DOT differential low power push-pull pair
1 - REF, 14.318MHz
Key Specifications:
CPU outputs cycle-cycle jitter < 85ps
SRC output cycle-cycle jitter < 125ps
+/- 100ppm frequency accuracy on all outputs
SRC are PCIe Gen2 compliant
Features/Benefits:
Supports spread spectrum modulation, default is 0.5%
down spread
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Does not require external pass transistor for voltage
regulator
Integrated 33series resistors on differential outputs,
Zo=50
Table 1: CPU Frequency Select Table
GNDXTAL
SEL_SATA_NS#
VDDXTAL
GNDREF
REF14.318M/FSLC**
VDDREF14M
CKPWRGD/PD#_3.3
VDDCPU
32 31 30 29 28 27 26 25
X1
1 24
CPUC0
X2 2
23
CPUT0
SMBCLK_3.3
3 22
GNDCPU
SMBDAT_3.3 4
21
SEL_120M#
VDD96 5
20
VDDSRC
DOT96T
6 19
SRC2C
DOT96C
7 18
SRC2T
GND96 8
17
GNDSRC
9 10 11 12 13 14 15 16
GNDSSC
CK_SSC_DISP_T
CK_SSC_DISP_C
VDDSSC
VDDSATA
SRC1T/SATA_NS_T
SRC1C/SATA_NS_C
GNDSATA
** Internal Pull-Down Resistor
9LRS4103
FS
L
C
B0b7
CPU
MHz
SRC
MHz
REF
MHz
DOT
MHz
0 (Default) 133.33
1 100.00
1. FS
L
C is a low-threshold input.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
100.00 14.318 96.00
SEL_120M#
Pin# 21 Pin# 10/11
Pulled Low 120MHz
Pulled High 100MHz
SEL_SATA_NS#
Pin# 31 Pin# 14/15
0 100MHz_nonSS
1 100MHz_SS
IDT
®
PC MAIN CLOCK 1520A—03/16/10
ICS9LRS4103
PC MAIN CLOCK
2
Pin Description
Pin# Pin Name Type Pin Description
1 X1 IN Crystal input, Nominally 14.318MHz.
2 X2 OUT Crystal output, Nominally 14.318MHzMHz.
3 SMBCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
4 SMBDAT_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
5 VDD96 PWR Power pin for the DOT96MHz output 3.3V.
6 DOT96T OUT
True clock DOT96 output with integrated 33ohm series resistor. No 50ohm
resistor to GND needed.
7 DOT96C OUT
Complementary clock DOT96 output with integrated 33ohm series resistor.
No 50ohm resistor to GND needed.
8 GND96 PWR Ground pin for the DOT96MHz output.
9 GNDSSC PWR Ground pin for the CK_SSC_DISP output.
10 CK_SSC_DISP_T OUT
True clock of CK_SSC_DISP (100MHz or 120MHz) output with integrated
33ohm series resistor. No 50ohm resistor to GND needed.
11 CK_SSC_DISP_C OUT
Complementary clock of CK_SSC_DISP (100MHz or 120MHz) output with
integrated 33ohm series resistor. No 50ohm resistor to GND needed.
12 VDDSSC PWR Power pin for the CK_SSC_DISP output 3.3V
13 VDDSATA PWR Power pin for the SATA output 3.3V
14 SRC1T/SATA_NS_T OUT
True clock of differential 0.8V push-pull SRC/SATA output with integrated
33ohm series resistor. No 50ohm resistor to GND needed.
15 SRC1C/SATA_NS_C OUT
Complementary clock of differential 0.8V push-pull SRC/SATA output with
integrated 33ohm series resistor. No 50ohm resistor to GND needed.
16 GNDSATA PWR Ground pin for the SATA output.
17 GNDSRC PWR Ground pin for the SRC output.
18 SRC2T OUT
True clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
19 SRC2C OUT
Complementary clock of differential 0.8V push-pull SRC output with
integrated 33ohm series resistor. No 50ohm resistor to GND needed.
20 VDDSRC PWR Power pin for the SRC output 3.3V.
21 SEL_120M# IN Selects pins #10/11 to be 120MHz or 100MHz. "0" = 120MHz, "1" = 100MHz.
22 GNDCPU PWR Ground pin for the CPU output.
23 CPUT0 OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
24 CPUC0 OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.
25 VDDCPU PWR Power pin for the CPU output 3.3V
26 CKPWRGD/PD#_3.3 IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN#
mode
27 VDDREF14M PWR Power pin for the REF output 3.3V
28 REF14.318M_3X/FSLC** I/O
Reference 14.318 MHz clock, which drives 3 loads on default / 3.3V tolerant
input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values.
29 GNDREF PWR Ground pin for the REF output.
30 VDDXTAL PWR Power pin for XTAL 3.3V
31 SEL_SATA_NS# IN Selects pin #14/15 to be SRC1 or SATA_NS. "0" = SATA_NS, "1" = SRC1
32 GNDXTAL PWR Ground pin for XTAL.
IDT
®
PC MAIN CLOCK 1520A—03/16/10
ICS9LRS4103
PC MAIN CLOCK
3
ICS9LRS4103 is compatible with the Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for
Intel desktop 5 series chipsets. ICS9LRS4103 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial
ATA and PCI-Express support.
General Description
Block Diagram
PLL2
DOT96
(Non-SS)
PLL1
CPU/SRC
(SS)
Div
Div
Div
Div
CPU
100/133MHz
SRC
100MHz
SATA
(non-SS/SS)
100MHz
DOT96MHz
(non-SS)
REF
14.318MHz
PLL3
SSC_DISP
(SS)
SSC_DISP
120/100MHz
14.318M

9LRS4103BKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK - PIKETON
Lifecycle:
New from this manufacturer.
Delivery:
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