IDT
®
PC MAIN CLOCK 1520A—03/16/10
ICS9LRS4103
PC MAIN CLOCK
10
General SMBus serial interface information for the ICS9LRS4103
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends the beginning byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X
(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
P stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
IDT
®
PC MAIN CLOCK 1520A—03/16/10
ICS9LRS4103
PC MAIN CLOCK
11
Byte 0 FS Readback and PLL Selection Register
Bit Pin Name Description Type 0 1 Default
7 FSLC CPU Freq. Sel. Bit
R
Latch
6 Reserved
Reserved
RW
-
-
0
5 Reserved
Reserved
RW
-
-
1
4 iAMT_EN Set via SMBus
RW
(Sticky 1)
Legacy Mode iAMT Enabled 0
3 Reserved
Reserved
RW
0
2 SEL_120M#
Selects pins #10/11 to be 120MHz or 100MHz
R
120MHz
100MHz
Latch
1 SEL_SATA_NS# Select source for SATA clock
R
SATA
(100MHz_nonSS)
SRC1
(100MHz SS)
Latch
0 PD_Restore
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-
on and go to latches open state
This bit is ignored and treated at '1' if device is in
iAMT mode.
RW
Configuration Not
Saved
Configuration
Saved
1
Byte 1 CPU/SRC Spread Selection Register
Bit Pin Name Description Type 0 1 Default
7 Reserved Reserved RW - - 0
6 CK505 PLL1_SSC_SEL
Select 0.5% down or center SSC
RW
Down spread
Center spread
0
5 Reserved
Reserved
RW
-
-
0
4 Reserved
Reserved
RW
-
-
0
3 Reserved Reserved RW - - 0
2 Reserved
Reserved
RW
-
-
0
1 Reserved
Reserved
RW
-
-
1
0 Reserved Reserved RW - - 1
Byte 2 Output Enable Register
Bit Pin Name Description Type 0 1 Default
7 REF_3L_OE
Output enable for REF0
RW
Output Disabled
Output Enabled
1
6 Reserved
Reserved
RW
-
-
1
5 Reserved
Reserved
RW
-
-
1
4 Reserved Reserved RW - - 1
3 Reserved
Reserved
RW
-
-
1
2 Reserved
Reserved
RW
-
-
1
1 Reserved
Reserved
RW
-
-
1
0 Reserved Reserved RW - - 1
Byte 3 Reserved Register
Bit Pin Name Description Type 0 1 Default
7 Reserved
Reserved
RW
-
-
1
6 Reserved
Reserved
RW
-
-
1
5 Reserved
Reserved
RW
-
-
1
4 Reserved Reserved RW - - 1
3 Reserved
Reserved
RW
-
-
1
2 Reserved
Reserved
RW
-
-
1
1 Reserved
Reserved
RW
1
0 Reserved Reserved RW - - 1
IDT
®
PC MAIN CLOCK 1520A—03/16/10
ICS9LRS4103
PC MAIN CLOCK
12
Byte 4 Output and Spread Spectrum Enable Register
Bit Pin Name Description Type 0 1 Default
7 CK_SSC_DISP Output enable for CK_SSC_DISP RW Output Disabled Output Enabled 1
6 SATA/SRC1_OE
Output enable for SATA/SRC1
RW
Output Disabled
Output Enabled
1
5 SRC2_OE
Output enable for SRC2
RW
Output Disabled
Output Enabled
1
4 DOT96_OE
Output enable for DOT96
RW
Output Disabled
Output Enabled
1
3 Reserved Reserved RW - - 1
2 CPU0_OE
Output enable for CPU0
RW
Output Disabled
Output Enabled
1
1 PLL1_SSC_ON
Enable PLL1's spread modulation
RW
Spread Disabled
Spread Enabled
1
0 PLL3_SSC_ON Enable PLL3's spread modulation RW Spread Disabled Spread Enabled 1
Byte 5 Reserved Register
Bit Pin Name Description Type 0 1 Default
7 Reserved
Reserved
RW
-
-
0
6 Reserved
Reserved
RW
-
-
0
5 Reserved Reserved RW - - 0
4 Reserved
Reserved
RW
-
-
0
3 Reserved
Reserved
RW
-
-
0
2 Reserved
Reserved
RW
-
-
0
1 Reserved Reserved RW - - 0
0 Reserved Reserved RW - - 0
Byte 6 Reserved Register
Bit Pin Name Description Type 0 1 Default
7 Reserved
Reserved
RW
-
-
0
6 Reserved Reserved RW - - 0
5 Reserved
Reserved
RW
-
-
0
4 Reserved
Reserved
RW
-
-
0
3 Reserved
Reserved
RW
-
-
0
2 Reserved Reserved RW - - 0
1 Reserved
Reserved
RW
-
-
0
0 Reserved Reserved RW - - 0
Byte 7 Vendor ID/ Revision ID
Bit Pin Name Description Type 0 1 Default
7 Rev Code Bit 3 R X
6 Rev Code Bit 2 R X
5 Rev Code Bit 1 R X
4 Rev Code Bit 0 R X
3 Vendor ID bit 3 R 0
2 Vendor ID bit 2 R 0
1 Vendor ID bit 1 R 0
0 Vendor ID bit 0 R 1
Byte 8 Device ID and Output Enable Register
Bit Pin Name Description Type 0 1 Default
7
Device_ID3 R 1
6
Device_ID2 R 0
5
Device_ID1 R 0
4
Device_ID0 R 0
3 Reserved
Reserved
RW
-
-
0
2 Reserved
Reserved
RW
-
-
0
1 Reserved
Reserved
RW
-
-
0
0 Reserved Reserved RW - - 0
Revision ID
Vendor specific
Table of Device identifier codes, used for
differentiating between CK505 package options,
etc.
32-pin device
Vendor ID
ICS is 0001, binary

9LRS4103BKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK - PIKETON
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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