LT5528
10
5528f
LO Section
The internal LO input amplifi er performs single-ended to
differential conversion of the LO input signal. Figure 4
shows the equivalent circuit schematic of the LO input.
Table 1. LO Port Input Impedance vs Frequency for EN = High
Frequency Input Impedance S
11
MHz Ω Mag Angle
1000 49.9 + j18.5 0.182 80
1400 68.1 + j8.8 0.171 22
1600 71.0 + j2.0 0.175 4.8
1800 70.0 j8.6 0.182 –6.6
2000 62.0 j12.8 0.156 –40
2200 53.8 j13.6 0.135 –66
2400 47.3 j12.4 0.128 –95
2600 41.1 j12.0 0.161 –119
If the part is in shut-down mode, the input impedance of
the LO port will be different. The LO input impedance for
EN = Low is given in Table 2.
Table 2. LO Port Input Impedance vs Frequency for EN = Low
Frequency Input Impedance S
11
MHz Ω Mag Angle
1000 46.6 + j47.6 0.443 67.8
1400 136 + j44.5 0.507 13.8
1600 157 j24.5 0.526 –6.2
1800 114 j70.6 0.533 –24.6
2000 70.7 j72.1 0.533 –43.2
2200 45.3 j59.0 0.528 –62.8
2400 31.2 j45.2 0.527 –83.5
2600 22.8 j34.2 0.543 –103
RF Section
After up-conversion, the RF outputs of the I and Q mixers are
combined. An on-chip balun performs internal differential
to single-ended output conversion, while transforming the
output signal impedance to 50Ω. Table 3 shows the RF
port output impedance vs. frequency.
Table 3. RF Port Output Impedance vs Frequency for EN = High
and P
LO
= 0dBm
Frequency Output Impedance S
22
MHz Ω Mag Angle
1000 23.1 + j7.9 0.382 158
1400 34.4 + j20.7 0.298 113
1600 45.8 + j22.3 0.231 87.6
1800 54.5 + j12.4 0.125 63.2
2000 48.7 + j1.7 0.022 127
2200 39.1 + j1.0 0.123 174
2400 32.9 + j4.4 0.213 163
2600 29.7 + j7.4 0.269 155
LO
INPUT
20pF
Z
IN
57
5528 F04
V
CC
The internal, differential LO signal is then split into in-
phase and quadrature (90° phase shifted) signals that
drive LO buffer sections. These buffers drive the double
balanced I and Q mixers. The phase relationship between
the LO input and the internal in-phase LO and quadrature
LO signals is fi xed, and is independent of start-up condi-
tions. The phase shifters are designed to deliver accurate
quadrature signals for an LO frequency near 2GHz. For
frequencies signifi cantly below 1.8GHz or above 2.4GHz,
the quadrature accuracy will diminish, causing the image
rejection to degrade. The LO pin input impedance is about
50Ω, and the recommended LO input power is 0dBm. For
lower LO input power, the gain, OIP2, OIP3 and dynamic-
range will degrade, especially below –5dBm and at T
A
=
85°C. For high LO input power (e.g. 5dBm), the LO feed-
through will increase with no improvement in linearity or
gain. Harmonics present on the LO signal can degrade the
image rejection because they can introduce a small excess
phase shift in the internal phase splitter. For the second (at
4GHz) and third harmonics (at 6GHz) at –20dBc level, the
introduced signal at the image frequency is about –56dBc
or lower, corresponding to an excess phase shift much
below 1 degree. For the second and third harmonics at
–10dBc, the introduced signal at the image frequency is
about –47dBc. Higher harmonics than the third will have
less impact. The LO return loss typically will be better than
17dB over the 1.7GHz to 2.3GHz range. Table 1 shows the
LO port input impedance vs. frequency.
Figure 4. Equivalent Circuit Schematic of the LO Input
APPLICATIO S I FOR ATIO
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LT5528
11
5528f
The RF output S
22
with no LO power applied is given in
Table 4.
Table 4. RF Port Output Impedance vs Frequency for EN = High
and No LO Power Applied
Frequency Output Impedance S
22
MHz Ω Mag Angle
1000 23.7 + j8.1 0.371 157
1400 37.7 + j18.5 0.248 112
1600 47.0 + j14.3 0.149 93.6
1800 46.0 + j5.5 0.071 123
2000 39.2 + j3.7 0.127 159
2200 34.2 + j6.2 0.201 154
2400 31.0 + j9.4 0.260 147
2600 29.6 + j11.6 0.292 142
For EN = Low the S
22
is given in Table 5.
Table 5. RF Port Output Impedance vs Frequency for EN = Low
Frequency Output Impedance S
22
MHz Ω Mag Angle
1000 22.8 + j7.7 0.386 158
1400 32.4 + j20.8 0.321 116
1600 42.4 + j25.1 0.274 91.7
1800 54.6 + j20.1 0.193 66.2
2000 55.3 + j6.0 0.076 45.3
2200 44.7 + j0.0 0.056 180
2400 36.0 + j1.9 0.164 171
2600 31.3 + j4.8 0.237 162
To improve S
22
for lower frequencies, a shunt capacitor
can be added to the output. At higher frequencies, a shunt
inductor can improve the S
22
. Figure 5 shows the equivalent
circuit schematic of the RF output.
Note that an ESD diode is connected internally from
the RF output to ground. For strong output RF signal
levels (higher than 3dBm), this ESD diode can degrade
the linearity performance if the 50Ω termination imped-
ance is connected directly to ground. To prevent this, a
coupling capacitor can be inserted in the RF output line.
This is strongly recommended during a 1dB compression
measurement.
Enable Interface
Figure 6 shows a simplifi ed schematic of the EN pin in-
terface. The voltage necessary to turn on the LT5528 is
1V. To disable (shut down) the chip, the Enable voltage
must be below 0.5V. If the EN pin is not connected, the
chip is disabled. This EN = Low condition is guaranteed
by the 75k on-chip pull-down resistor. It is important that
the voltage at the EN pin does not exceed V
CC
by more
than 0.5V. If this should occur, the supply current could
be sourced through the EN pin ESD protection diodes,
which are not designed to carry the full supply current,
and damage may result.
Figure 7. Evaluation Circuit SchematicFigure 5. Equivalent Circuit Schematic of the RF Output
Figure 6. EN Pin Interface
RF
OUTPUT
20pF
21pF3nH
52.5
5528 F05
V
CC
Evaluation Board
Figure 7 shows the evaluation board schematic. A good
ground connection is required for the exposed pad. If this
is not done properly, the RF performance will degrade.
EN
75k
5528 F06
V
CC
25k
BBIPBBIM
J1
16 15 14 13
V
CC
V
CC
EN
9
10
11
12
4
3
2
1
5678
5528 F07
17
BBQM
BBQP
BOARD NUMBER: DC729A
C1
100nF
J6
RF
OUT
J3
LO
IN
J4
GND
J5
C2
100nF
J2
BBMI
LT5528
BBPI V
CC
BBMQ GND
GND
BBPQ V
CC
GND
GND
RF
GND
GND
LO
GND
EN
GND
100
R1
APPLICATIO S I FOR ATIO
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LT5528
12
5528f
Additionally, the exposed pad provides heat sinking for the
part and minimizes the possibility of the chip overheating.
If improved LO and Image suppression are required, an LO
feed-through calibration and an Image suppression calibra-
tion can be performed. The evaluation board schematic
of the calibration hardware, the calibration procedure and
the results are described in an application note.
R1 (optional) limits the Enable pin current in the event
that the Enable pin is pulled high while the V
CC
inputs are
low. In Figures 8, 9, 10 and 11, the silk screens and the
PCB board layout are shown.
Figure 8. Component Side Silk Screen of Evaluation Board
Figure 10. Bottom Side Silk Screen of Evaluation Board
Figure 9. Component Side Layout of Evaluation Board
Figure 11. Bottom Side Layout of Evaluation Board
APPLICATIO S I FOR ATIO
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LT5528EUF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Modulator / Demodulator 2GHz Direct Quadrature Modulator
Lifecycle:
New from this manufacturer.
Delivery:
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