AX8052F131
www.onsemi.com
15
CIRCUIT DESCRIPTION
The AX8052F131 is a single chip ultra−low−power
RF−microcontroller SoC primarily for use in SRD bands.
The on−chip transmitter consists of a fully integrated RF
front−end with modulator, and demodulator. Base band data
processing is implemented in an advanced and flexible
communication controller that enables user friendly
communication.
The AX8052F131 contains a high speed microcontroller
compatible to the industry standard 8052 instruction set. It
contains 64 kBytes of FLASH and 8.25 kBytes of internal
SRAM.
The AX8052F131 features 3 16−bit general purpose
timers with SD capability, 2 output compare units for
generating PWM signals, 2 input compare units to record
timings of external signals, 2 16−bit wakeup timers, a
watchdog timer, 2 UARTs, a Master/Slave SPI controller, a
10−bit 500 kSample/s A/D converter, 2 analog comparators,
a temperature sensor, a 2 channel DMA controller, and a
dedicated AES crypto controller. Debugging is aided by a
dedicated hardware debug interface controller that connects
using a 3−wire protocol (1 dedicated wire, 2 shared with
GPIO) to the PC hosting the debug software.
While the radio carrier can only be clocked by the crystal
oscillator (carrier stability requirements dictate a high
stability reference clock in the MHz range), the
microcontroller and its peripherals provide extremely
flexible clocking options. The system clock that clocks the
microcontroller, as well as peripheral clocks, can be selected
from one of the following clock sources: the crystal
oscillator, an internal high speed 20 MHz oscillator, an
internal low speed 640 Hz/10 kHz oscillator, or the low
frequency crystal oscillator. Prescalers offer additional
flexibility with their programmable divide by a power of two
capability. To improve the accuracy of the internal
oscillators, both oscillators may be slaved to the crystal
oscillator.
AX8052F131 can be operated from a 2.2 V to 3.6 V power
supply over a temperature range of –40°C to 85°C, it
consumes 11 − 45 mA for transmitting, depending on the
output power.
The AX8052F131 features make it an ideal interface for
integration into various battery powered SRD solutions such
as ticketing or as transmitter for telemetric applications e.g.
in sensors. As primary application, the transmitter is
intended for UHF radio equipment in accordance with the
European Telecommunication Standard Institute (ETSI)
specification EN 300 220−1 and the US Federal
Communications Commission (FCC) standard CFR47, part
15. The use of AX8052F131 in accordance to FCC Par
15.247, allows for improved range in the 915 MHz band.
Additionally AX8052F131 is compatible with the low
frequency standards of 802.15.4 (ZigBee) and suited for
systems targeting compliance with Wireless M−Bus
standard EN 13757−4:2005
The AX8052F131 sends data in frames. This standard
operation mode is called Frame Mode. Pre and post ambles
as well as checksums can be generated automatically.
AX8052F131 supports any data rate from 1 kbps to
350 kbps for FSK and MSK, from 1 kbps to 2000 kbps for
ASK and from 10 kbps to 2000 kbps for PSK. To achieve
optimum performance for specific data rates and
modulation schemes several register settings to configure
the AX8052F131 are necessary, they are outlined in the
following, for details see the AX5031 Programming
Manual.
Spreading is possible on all data rates and modulation
schemes. The net transfer rate is reduced by a factor of 15 in
this case. For ZigBee either 600 or 300 kbps modes have to
be chosen.
The transmitter supports multi−channel operation for all
data rates and modulation schemes.
Microcontroller
The AX8052 microcontroller core executes the industry
standard 8052 instruction set. Unlike the original 8052,
many instructions are executed in a single cycle. The system
clock and thus the instruction rate can be programmed freely
from DC to 20 MHz.
Memory Architecture
The AX8052 Microcontroller features the highest
bandwidth memory architecture of its class. Figure 4 shows
the memory architecture. Three bus masters may initiate bus
cycles:
• The AX8052 Microcontroller Core
• The Direct Memory Access (DMA) Engine
• The Advanced Encryption Standard (AES) Engine
Bus targets include:
• Two individual 4 kBytes RAM blocks located in X
address space, which can be simultaneously accessed
and individually shut down or retained during sleep
mode
• A 256 Byte RAM located in internal address space,
which is always retained during sleep mode
• A 64 kBytes FLASH memory located in code space.
• Special Function Registers (SFR) located in internal
address space accessible using direct address mode
instructions
• Additional Registers located in X address space
(X Registers)
The upper half of the FLASH memory may also be
accessed through the X address space. This simplifies and
makes the software more efficient by reducing the need for
generic pointers.
NOTE: Generic pointers include, in addition to the
address, an address space tag.
