AX8052F131
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25
APPLICATION INFORMATION
Typical Application Diagrams
Connecting to Debug Adapter
Figure 9. Typical Application Diagram with Connection to the Debug Adapter
CLK16P
CLK16N
VDDA
GND
ANTP
ANTN
GND
GND
VREG
PC7
PA7
PA6
PA5
PA4
DBG_EN
PB7
PB4
SYSCLK
T1
T2
T1
PC3
PC2
SYSCLK
VDDA
PB3
PA3
PA2
PA1
PA0
VDD_IO
PC1
PC0
PB0
PB2
PB1
AX8052F131
100pF
4.7uF
DBG_EN
DBG_RT_N
GND
DBG_CLK
DBG_DATA
GND
DBG_VDD
Jumper JP1
1
2
3
4
5
6
7
8
32 kHz XTAL
Debug adapter
connector
1uF
VDD_IO
16 MHz
XTAL
Short Jumper JP1−1 if it is desired to supply the target
board from the Debug Adapter (50 mA max). Connect the
bottom exposed pad of the AX8052F131 to ground.
If the debugger is not running, PB6 and PB7 are not driven
by the Debug Adapter. If the debugger is running, the PB6
and PB7 values that the software reads may be set using the
Pin Emulation feature of the debugger.
PB3 is driven by the debugger only to bring the
AX8052F131 out of Deep Sleep. It is high impedance
otherwise.
The 32 kHz crystal is optional, the fast crystal at pins
CLK16N and CLK16P is used as reference frequency for the
RF RX/TX. Crystal load capacitances should be chosen
according to the crystal’s datasheet. At pins CLK16N and
CLK16P they the internal programmable capacitors may be
used, at pins PA3 and PA4 capacitors must be connected
externally.
It is mandatory to add 1 mF (low ESR) between VREG and
GND. Decoupling capacitors are not all drawn. It is
recommended to add 100 nF decoupling capacitor for every
VDDA and VDD_IO pin. In order to reduce noise on the
antenna inputs it is recommended to add 27 pF on the VDD
pins close to the antenna interface.
The AX8052F131 has an integrated voltage regulator for
the analog supply voltages, which generates a stable supply
voltage VREG from the voltage applied at VDD_IO. Use
VREG to supply all the VDDA supply pins and also to DC
power to the pins ANTP and ANTN.
