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Table 1. PIN FUNCTION DESCRIPTIONS
Symbol Pin(s) Type Description
CLK16P 1 A Crystal oscillator input/output (RF reference)
CLK16N 2 A Crystal oscillator input/output (RF reference)
VDDA 3 P Power supply, must be supplied with regulated voltage VREG
GND 4 P Ground
ANTP 5 A Antenna output
ANTN 6 A Antenna output
GND 7 P Ground
VDDA 8 P Power supply, must be supplied with regulated voltage VREG
SYSCLK 9 I/O/PU Must be connected to SYSCLK at pin 13
T1 10 I/O/PU Must be connected to T1 at pin 12
T2 11 I/O/PU Must be left unconnected
T1 12 I/O/PU Must be connected to T1 at pin 10
SYSCLK 13 I/O/PU Must be connected to SYSCLK at pin 9
PC3 14 I/O/PU General Purpose IO
PC2 15 I/O/PU General Purpose IO
PC1 16 I/O/PU General Purpose IO
PC0 17 I/O/PU General Purpose IO
PB0 18 I/O/PU General Purpose IO
PB1 19 I/O/PU General Purpose IO
PB2 20 I/O/PU General Purpose IO
PB3 21 I/O/PU General Purpose IO
PB4 22 I/O/PU General Purpose IO
PB5 23 I/O/PU General Purpose IO
PB6 24 I/O/PU General Purpose IO, DBG_DATA
PB7 25 I/O/PU General Purpose IO, DBG_CLK
DBG_EN 26 I/PD InCircuit Debugger Enable
RESET_N 27 I/PU Optional reset pin
If this pin is not used it must be connected to VDD_IO
GND 28 P Ground
VDD_IO 29 P Unregulated power supply (battery input)
PA0 30 I/O/A/PU General Purpose IO
PA1 31 I/O/A/PU General Purpose IO
PA2 32 I/O/A/PU General Purpose IO
PA3 33 I/O/A/PU General Purpose IO
PA4 34 I/O/A/PU General Purpose IO
PA5 35 I/O/A/PU General Purpose IO
PA6 36 I/O/A/PU General Purpose IO
PA7 37 I/O/A/PU General Purpose IO
PC7 38 I/O/PU General Purpose IO
VREG 39 P Regulated output voltage
VDDA pins must be connected to this supply voltage
A 1 mF low ESR capacitor to GND must be connected to this pin
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Table 1. PIN FUNCTION DESCRIPTIONS
Symbol DescriptionTypePin(s)
GND 40 P Ground
GND Center pad P Ground on center pad of QFN, must be connected
A = analog input
I = digital input signal
O = digital output signal
PU = pullup
I/O = digital input/output signal
N = not to be connected
P = power or ground
PD = pulldown
All digital inputs are Schmitt trigger inputs, digital input
and output levels are LVCMOS/LVTTL compatible. Port A
Pins (PA0 PA7) must not be driven above VDD_IO, all
other digital inputs are 5 V tolerant. Pullups are
programmable for all GPIO pins.
Alternate Pin Functions
GPIO Pins are shared with dedicated Input/Output signals
of onchip peripherals. The following table lists the
available functions on each GPIO pin.
Table 2. ALTERNATE PIN FUNCTIONS
GPIO Alternate Functions
PA0 T0OUT IC1 ADC0
PA1 T0CLK OC1 ADC1
PA2 OC0 U1RX ADC2 COMPI00
PA3 T1OUT ADC3 LPXTALP
PA4 T1CLK COMPO0 ADC4 LPXTALN
PA5 IC0 U1TX ADC5 COMPI10
PA6 T2OUT ADCTRIG ADC6 COMPI01
PA7 T2CLK COMPO1 ADC7 COMPI11
PB0 U1TX IC1 EXTIRQ0
PB1 U1RX OC1
PB2 IC0 T2OUT
PB3 OC0 T2CLK EXTIRQ1 DSWAKE
PB4 U0TX T1CLK
PB5 U0RX T1OUT
PB6 DBG_DATA
PB7 DBG_CLK
PC0 SSEL T0OUT EXTIRQ0
PC1 SSCK T0CLK COMPO1
PC2 SMOSI U0TX
PC3 SMISO U0RX COMPO0
PC7 RPWRUP
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Pinout Drawing
Figure 2. Pinout Drawing (Top View)
AX8052F131
QFN40
8
7
6
5
4
3
2
1
9 10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
40 39 38 37 36 35 34 33 32 31 30 29
CLK16P
VDDA
CLK16N
GND
ANTP
ANTN
VDDA
GND
T1
T2
SYSCLK
COMPO0/U0RX/SMISO/PC3
U0TX/SMOSI/PC2
COMPO1/T0CLK/SSCK/PC1
EXTIRQ0/T0OUT/SSEL/PC0
EXTIRQ0/IC1/U1TX/PB0
OC1/U1RX/PB1
T2OUT/IC0/PB2
GND
VREG
PC7/RPWRUP
PA7/ADC7/T2CLK/COMPO1/COMPI11
PA6/ADC6/T2OUT/ADCTRIG/COMPI01
PA5/ADC5/IC0/U1TX/COMPI10
PA4/ADC4/T1CLK/COMPO0/LPXTALN
PA3/ADC3/T1OUT/LPXTALP
PA2/ADC2/OC0/U1RX/COMPI00
PA1/ADC1/T0CLK/OC1
PA0/ADC0/T0OUT/IC1
VDD_IO
GND
RESET_N
DBG_EN
PB7/DBG_CLK
PB6/DBG_DATA
PB5/U0RX/T1OUT
PB4/U0TX/T1CLK
PB3/OC0/T2CLK/EXTIRQ1/DSWAKE
SYSCLK
T1

AX8052F131-2-TX30

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU RF-MICROCONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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