AX8052F131-2-TX30 Datasheet AX8052F131-2-TB05, AX8052F131-2-TX30 | P22-P24

AX8052F131

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TRANSMITTER

The transmitter block is controllable through its registers,

which are mapped into the X data space of the

micro−controller. The transmitter block features its own

32 word × 10 bit FIFO. The microcontroller can either be

interrupted at a programmable FIFO fill level, or one of the

DMA channels can be instructed to transfer between XRAM

and the transmitter FIFO.

RF Frequency Generation Subsystem

The RF frequency generation subsystem consists of a

fully integrated synthesizer, which multiplies the reference

frequency from the crystal oscillator to get the desired RF

frequency. The advanced architecture of the synthesizer

enables frequency resolutions of 1 Hz, as well as fast settling

times of 5 – 50 ms depending on the settings (see section AC

Characteristics). Fast settling times mean fast start−up,

which enables low−power system design.

The frequency must be programmed to the desired carrier

frequency.

The synthesizer loop bandwidth can be programmed, this

serves three purposes:

1. Start−up time optimization, start−up is faster for

higher synthesizer loop bandwidths

2. TX spectrum optimization, phase−noise at

300 kHz to 1 MHz distance from the carrier

improves with lower synthesizer loop bandwidths

3. Adaptation of the bandwidth to the data−rate. For

transmission of FSK and MSK it is required that

the synthesizer bandwidth must be in the order of

the data−rate.

VCO

An on−chip VCO converts the control voltage generated

by the charge pump and loop filter into an output frequency.

The frequency can be programmed in 1 Hz steps in the

AX5031_FREQ registers. For operation in the 433 MHz

band, the BANDSEL bit in the AX5031_PLLLOOP

VCO Auto−Ranging

The AX8052F131 has an integrated auto−ranging

function, which allows to set the correct VCO range for

specific frequency generation subsystem settings

automatically. Typically it has to be executed after

power−up. The function is initiated by setting the

RNG_START bit in the AX5031_PLLRANGING register.

The bit is readable and a 0 indicates the end of the ranging

process. The RNGERR bit indicates the correct execution of

the auto−ranging.

Loop Filter and Charge Pump

The AX8052F131 internal loop filter configuration

together with the charge pump current sets the synthesizer

loop band width. The loop−filter has three configurations

that can be programmed via the register bits FLT[1:0] in

be programmed using register bits PLLCPI[1:0] also in

typically 50 – 500 kHz depending on the

AX5031_PLLLOOP settings, for details see the section:

AC Characteristics.

Registers

Table 16. REGISTERS

AX5031_PLLLOOP

FLT[1:0] Synthesizer loop filter bandwidth, recommended usage is to increase the bandwidth for faster

settling time, bandwidth increases of factor 2 and 5 are possible.

PLLCPI[2:0] Synthesizer charge pump current, recommended usage is to decrease the bandwidth (and im-

prove the phase−noise) for low data−rate transmissions.

BANDSEL Switches between 868 MHz / 915 MHz and 433 MHz bands

AX5031_FREQ Programming of the carrier frequency

AX5031_FREQB Programming of the 2

carrier frequency, switch to this carrier frequency by setting bit FRE-

QSEL = 1

AX5031_PLLRANGING Initiate VCO auto−ranging and check results

RF Input and Output Stage (ANTP/ANTN)

The AX8052F131 uses fully differential antenna pins.

The PA drives the signal generated by the frequency

generation subsystem out to the differential antenna

terminals. The output power of the PA is programmed via

bits TXRNG[3:0] in the register AX5031_TXPWR. Output

power as well as harmonic content will depend on the

external impedance seen by the PA, recommendations are

given in section: Antenna Interface Circuitry.

Encoder

The encoder is located between the Framing Unit and the

Modulator. It can optionally transform the bit−stream in the

following ways:

• It can invert the bit stream.

• It can perform differential encoding. This means that a

zero is transmitted as no change in the level, and a one

is transmitted as a change in the level. Differential

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encoding is useful for PSK, because PSK transmissions

can be received either as transmitted or inverted, due to

the uncertainty of the initial phase. Differential

encoding / decoding removes this uncertainty.

• It can perform Manchester encoding. Manchester

encoding ensures that the modulation has no DC

content and enough transitions (changes from 0 to 1 and

from 1 to 0) for the demodulator bit timing recovery to

function correctly, but does so at a doubling of the data

rate.

• It can perform Spectral Shaping. Spectral shaping

removes DC content of the bit stream, ensures

transitions for the demodulator bit timing recovery, and

makes sure that the transmitted spectrum does not have

discrete lines even if the transmitted data is cyclic. It

does so without adding additional bits, i.e. without

changing the data rate. Spectral Shaping uses a self

synchronizing feedback shift register.

The encoder is programmed using the register

AX5031_ENCODING, details and recommendations on

usage are given in the AX5031 Programming Manual.

Framing and FIFO

Most radio systems today group data into packets. The

framing unit is responsible for converting these packets into

a bit−stream suitable for the modulator.

The Framing unit supports three different modes:

• HDLC

• Raw

• 802.15.4 compliant

The microcontroller communicates with the framing unit

through a 32 level × 10 bit FIFO. The FIFO decouples

microcontroller timing from the radio (modulator) timing.

The bottom 8 bits of the FIFO contain transmit data. The top

2 bits are used to convey meta information in HDLC and

802.15.4 modes. They are unused in Raw mode. The meta

information consists of packet begin / end information and

the result of CRC checks.

The FIFO can be operated in polled or interrupt driven

modes. In polled mode, the microcontroller must

periodically read the FIFO status register or the FIFO count

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT

FULL and programmable level interrupts are provided.

Interrupts are acknowledged by removing the cause for the

interrupt, i.e. by emptying or filling the FIFO.

To lower the interrupt load on the microcontroller, one of

the DMA channels may be instructed to transfer data

between the transmitter FIFO and the XRAM memory. This

way, much larger buffers can be realized in XRAM, and

interrupts need only be serviced if the larger XRAM buffers

fill or empty.

HDLC Mode

NOTE: HDLC mode follows High−Level Data Link

Control (HDLC, ISO 13239) protocol.

HDLC Mode is the main framing mode of the

AX8052F131. In this mode, the AX8052F131 performs

automatic packet delimiting, and optional packet

correctness check by inserting and checking a cyclic

redundancy check (CRC) field.

The packet structure is given in the following table.

Table 17.

Flag Address Control Information FCS Flag

8 bit 8 bit 8 or 16 bit Variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit

HDLC packets are delimited with flag sequences of

content 0x7E.

In AX8052F131 the meaning of address and control is

user defined. The Frame Check Sequence (FCS) can be

programmed to be CRC−CCITT, CRC−16 or CRC−32.

For details on implementing a HDLC communication see

the AX5031 Programming Manual.

Raw Mode

In Raw mode, the AX8052F131 does not perform any

packet delimiting or byte synchronization. It simply

serializes transmit bytes.

This mode is ideal for implementing legacy protocols in

software.

802.15.4 (ZigBee) DSSS

802.15.4 uses binary phase shift keying (PSK) with

300 kbit/s (868 MHz band) or 600 kbit/s (915 MHz band) on

the radio. The usable bit rate is only a 15

of the radio bit

rate, however. A spreading function in the transmitter

expands the user bit rate by a factor of 15, to make the

transmission more robust.

In 802.15.4 mode, the AX8052F131 framing unit

performs the spreading function according to the 802.15.4

specification.

The 802.15.4 is a universal DSSS mode, which can be

used with any modulation or data rate as long as it does not

violate the maximum data rate of the modulation being used.

Therefore the maximum DSSS data rate is 16 kbps for FSK

and 40 kbps for ASK and PSK.

AX8052F131

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Modulator

Depending on the transmitter settings the modulator generates various inputs for the PA:

Table 18.

Modulation Bit = 0 Bit = 1 Main Lobe Bandwidth Max. Bitrate

ASK PA off PA on BW = BITRATE 2000 kBit/s

FSK / MSK / GFSK

Df = −f

deviation

Df = +f

deviation

BW = (1 + h) ⋅BITRATE 350 kBit/s

PSK

DF = 0° DF = 180°

BW = BITRATE 2000 kBit/s

h = modulation index. It is the ratio of the

deviation compared to the bit−rate;

deviation

= 0.5⋅h⋅BITRATE, AX8052F131 can

demodulate signals with h < 32.

ASK = amplitude shift keying

FSK = frequency shift keying

MSK = minimum shift keying; MSK is a special case

of FSK, where h = 0.5, and therefore

deviation

= 0.25⋅BITRATE; the advantage of

MSK over FSK is that it can be demodulated

more robustly.

PSK = phase shift keying

OQPSK = offset quadrature shift keying. The

AX8052F131 supports OQPSK. However,

unless compatibility to an existing system is

required, MSK should be preferred.

4−FSK = four frequencies are used to transmit two bits

simultaneously during each symbol

All modulation schemes are binary.

Table 19.

Modulation Symbol = 00 Symbol = 01 Symbol = 10 Symbol = 11 Max. Bitrate

4−FSK

Df = −3⋅f

deviation

Df = −f

deviation

Df = +f

deviation

Df = +3⋅f

deviation

400 kBit/s

PWRMODE Register

The AX8052F131 transmitter features its own

independent power management, independent from the

microcontroller. While the microcontroller power mode is

controlled through the PCON register, the

AX5031_PWRMODE register controls which parts of the

transmitter are operating.

Table 20. PWRMODE REGISTER

AX5031_PWRMODE

Name Description

0000 POWERDOWN All digital and analog transmitter functions, except the register file, are disabled.

VREG is reduced to conserve leakage power. The registers are still accessible.

0100 VREGON All digital and analog transmitter functions, except the register file, are disabled.

VREG, however is at its nominal value for operation, and all registers are accessible.

0101 STANDBY The crystal oscillator is powered on; the transmitter is off.

1100 SYNTHTX The synthesizer is running on the transmit frequency. The transmitter is still off. This mode

is used to let the synthesizer settle on the correct frequency for transmit.

1101 FULLTX Synthesizer and transmitter are running. Do not switch into this mode before the synthesiz-

er has completely settled on the transmit frequency (in SYNTHTX mode), otherwise spuri-

ous spectral transmissions will occur.

Table 21. A TYPICAL AX5031_PWRMODE SEQUENCE FOR A TRANSMIT SESSION

Step PWRMODE [3:0] Remarks

1 POWERDOWN

2 STANDBY The settling time is dominated by the crystal used, typical value 3 ms.

4 SYNTHTX

The synthesizer settling time is 5 – 50 ms depending on settings, see section AC Characteristics

3 FULLTX Data transmission

4 POWERDOWN

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AX8052F131-2-TX30

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Microcontrollers - MCU 8-bit Microcontrollers - MCU RF-MICROCONTROLLER

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AX8052F131-2-TX30

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