Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
Single Cycle Reprogram (Erase and Program)
1024 Pages (264 Bytes/Page) Main Memory
Supports Page and Block Erase Operations
Two 264-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Continuous Read Capability through Entire Array
Ideal for Code Shadowing Applications
Low Power Dissipation
4 mA Active Read Current Typical
2 µA CMOS Standby Current Typical
Hardware Data Protection Feature
100% Compatible to AT45DB021 and AT45DB021A
5.0V-tolerant Inputs: SI, SCK, CS, RESET and WP Pins
Commercial and Industrial Temperature Ranges
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
1. Description
The AT45DB021B is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 2,162,688 bits of memory are organized as 1024 pages of 264 bytes each. In addi-
tion to the main memory, the AT45DB021B also contains two SRAM data buffers
of 264 bytes each. The buffers allow receiving of data while a page in the main mem-
ory is being reprogrammed, as well as reading or writing a continuous data stream.
EEPROM emulation (bit or byte alterability) is easily handled with a self-
contained three step Read-Modify-Write operation. Unlike conventional Flash
memories that are accessed randomly with multiple address lines and a parallel inter-
face, the DataFlash uses a SPI serial interface to sequentially access its data.
DataFlash supports SPI mode 0 and mode 3. The simple serial interface facilitates
hardware layout, increases system reliability, minimizes switching noise, and reduces
package size and active pin count. The device is optimized for use in many commer-
cial and industrial applications where high density, low pin count, low voltage, and low
power are essential. The device operates at clock frequencies up to 20 MHz with a
typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the AT45DB021B does not require
high input voltages for programming. The device operates from a single power supply,
2.7V to 3.6V, for both the program and read operations. The AT45DB021B is enabled
through the chip select pin (CS
) and accessed via a three-wire interface consisting of
the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
When the device is shipped from Atmel, the most significant page of the memory
array may not be erased. In other words, the contents of the last page may not be
filled with FFH.
2-megabit
2.7-volt Only
DataFlash
®
AT45DB021B
1937J–DFLSH–9/05
2
1937J–DFLSH–9/05
AT45DB021B
2. Pin Configurations and Pinouts
Table 2-1. Pin Configurations
Pin Name Function
CS
Chip Select
SCK Serial Clock
SI Serial Input
SO Serial Output
WP
Hardware Page Write Protect Pin
RESET Chip Reset
RDY/BUSY
Ready/Busy
Figure 2-1. TSOP Top View, Type 1 Figure 2-2. 8-SOIC
Figure 2-3. 28-SOIC
(1)
Note: 1. This package is not recommended for new designs.
Figure 2-4. CBGA Top View
through Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
8
7
6
5
SI
SCK
RESET
CS
SO
GND
VCC
WP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
123
VCC
WP
RESET
GND
RDY/BSY
SI
SCK
CS
SO
3
1937J–DFLSH–9/05
AT45DB021B
3. Block Diagram
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB021B is divided into three levels of
granularity comprised of sectors, blocks and pages. The Memory Architecture Diagram illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis; however, the optional
erase operations can be performed at the block or page level.
Figure 4-1. Memory Architecture Diagram
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
RDY/BUSY
WP
SOSI
SECTOR 0a = 8 Pages
2112 bytes (2K + 64)
SECTOR 0b = 248 Pages
65,472 bytes (62K + 1984)
Block = 2112 bytes
(2K + 64)
8 Pages
SECTOR 0
SECTOR 1
Page = 264 bytes
(256 + 8)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 1022
PAGE 1023
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 1021
BLOCK 1
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 126
BLOCK 127
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
SECTOR 2
BLOCK 2
SECTOR 0c = 256 Pages
67,584 bytes (64K + 2K)
SECTOR 1 = 512 Pages
135,168 bytes (128K + 4K)

AT45DB021B-SU

Mfr. #:
Manufacturer:
Description:
IC FLASH 2M SPI 20MHZ 8SOIC
Lifecycle:
New from this manufacturer.
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