OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AT45DB021B-SU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
7
1937J–DFLSH–9/05
AT45DB021B
5.2.4 Page Erase
The optional Page Erase command can be used to individually erase any page in the main
memory array allowing the Buffer to Main Memory Page Program without Built-in Erase com-
mand to be utilized at a later time. To perform a Page Erase, an opcode of 81H must be loaded
into the device, followed by five reserved bits, ten address bits (PA9-PA0), and nine don’t care
bits. The ten address bits are used to specify which page of the memory array is to be erased.
When a low-to-high transition occurs on the CS
pin, the part will erase the selected page to 1s.
The erase operation is internally self-timed and should take place in a maximum time of t
PE
. Dur-
ing this time, the status register will indicate that the part is busy.
5.2.5 Block Erase
A block of eight pages can be erased at one time allowing the Buffer to Main Memory Page Pro-
gram without Built-in Erase command to be utilized to reduce programming times when writing
large amounts of data to the device. To perform a Block Erase, an opcode of 50H must be
loaded into the device, followed by five reserved bits, seven address bits (PA9-PA3), and 12
don’t care bits. The seven address bits are used to specify which block of eight pages is to be
erased. When a low-to-high transition occurs on the CS
pin, the part will erase the selected
block of eight pages to 1s. The erase operation is internally self-timed and should take place in a
maximum time of t
BE
. During this time, the status register will indicate that the part is busy.
5.2.6 Main Memory Page Program through Buffer
This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program
with Built-in Erase operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and
then programmed into a specified page in the main memory. To initiate the operation, an 8-bit
opcode (82H for buffer 1 or 85H for buffer 2) must be followed by the five reserved bits and 20
address bits. The 10 most-significant address bits (PA9-PA0) select the page in the main mem-
ory where data is to be written, and the next nine address bits (BFA8-BFA0) select the first byte
in the buffer to be written. After all address bits are shifted in, the part will take data from the SI
pin and store it in one of the data buffers. If the end of the buffer is reached, the device will wrap
around back to the beginning of the buffer. When there is a low-to-high transition on the CS
pin,
the part will first erase the selected page in main memory to all 1s and then program the data
stored in the buffer into the specified page in the main memory. Both the erase and the program-
ming of the page are internally self-timed and should take place in a maximum of time t
EP
.
During this time, the status register will indicate that the part is busy.
Table 5-2. Block Erase Addressing
PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block
0000000XXX 0
0000001XXX 1
0000010XXX 2
0000011XXX 3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1111100XXX124
1111101XXX125
1111110XXX126
1111111XXX127
8
1937J–DFLSH–9/05
AT45DB021B
5.3 Additional Commands
5.3.1 Main Memory Page to Buffer Transfer
A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start
the operation, an 8-bit opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the
five reserved bits, 10 address bits (PA9-PA0) which specify the page in main memory that is to
be transferred, and nine don’t care bits. The CS
pin must be low while toggling the SCK pin to
load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of the
page of data from the main memory to the buffer will begin when the CS
pin transitions from a
low to a high state. During the transfer of a page of data (t
XFR
), the status register can be read to
determine whether the transfer has been completed or not.
5.3.2 Main Memory Page to Buffer Compare
A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate
the operation, an 8-bit opcode (60H for buffer 1 and 61H for buffer 2) must be followed by 24
address bits consisting of the five reserved bits, 10 address bits (PA9-PA0) which specify the
page in the main memory that is to be compared to the buffer, and nine don’t care bits. The CS
pin must be low while toggling the SCK pin to load the opcode, the address bits and the don’t
care bits from the SI pin. On the low-to-high transition of the CS
pin, the 264 bytes in the
selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2. During
this time (t
XFR
), the status register will indicate that the part is busy. On completion of the com-
pare operation, bit 6 of the status register is updated with the result of the compare.
5.3.3 Auto Page Rewrite
This mode is needed only if multiple bytes within a page or multiple pages of data are modified in
a random fashion. This mode is a combination of two operations: Main Memory Page to Buffer
Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first
transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1
or buffer 2) is programmed back into its original page of main memory. To start the rewrite oper-
ation, an 8-bit opcode (58H for buffer 1 or 59H for buffer 2) must be followed by the five reserved
bits, 10 address bits (PA9-PA0) that specify the page in main memory to be rewritten, and nine
additional don’t care bits. When a low-to-high transition occurs on the CS
pin, the part will first
transfer data from the page in main memory to a buffer and then program the data from the
buffer back into same page of main memory. The operation is internally self-timed and should
take place in a maximum time of t
EP
. During this time, the status register will indicate that the
part is busy.
If a sector is programmed or reprogrammed sequentially page-by-page, then the programming
algorithm shown in Figure 15-1 on page 25 is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in Figure 15-2 on page 26 is recommended. Each page within a sector must be
updated/rewritten at least once within every 10,000 cumulative page erase/program operations
in that sector.
9
1937J–DFLSH–9/05
AT45DB021B
5.4 Operation Mode Summary
The modes described can be separated into two groups – modes which make use of the Flash
memory array (Group A) and modes which do not make use of the Flash memory array (Group
B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer 1 (or 2) Transfer
3. Main Memory Page to Buffer 1 (or 2) Compare
4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase
5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program through Buffer
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
If a Group A mode is in progress (not fully completed), then another mode in Group A should not
be started. However, during this time in which a Group A mode is in progress, modes in Group B
can be started.
This gives the Serial DataFlash the ability to virtually accommodate a continuous data stream.
While data is being programmed into main memory from buffer 1, data can be loaded into buffer
2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
Table 5-3. Read Commands
Command SCK Mode Opcode
Continuous Array Read
Inactive Clock Polarity Low or High 68H
SPI Mode 0 or 3 E8H
Main Memory Page Read
Inactive Clock Polarity Low or High 52H
SPI Mode 0 or 3 D2H
Buffer 1 Read
Inactive Clock Polarity Low or High 54H
SPI Mode 0 or 3 D4H
Buffer 2 Read
Inactive Clock Polarity Low or High 56H
SPI Mode 0 or 3 D6H
Status Register Read
Inactive Clock Polarity Low or High 57H
SPI Mode 0 or 3 D7H
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

AT45DB021B-SU

Mfr. #:
Buy AT45DB021B-SU
Manufacturer:
Description:
IC FLASH 2M SPI 20MHZ 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet