13
1937J–DFLSH–9/05
AT45DB021B
Note: 1. After power is applied and V
CC
is at the minimum specified datasheet value, the system should wait 20 ms before an
operational mode is started.
Note: 1. I
cc1
during a buffer read is 20mA maximum.
7. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
8. DC and AC Operating Range
AT45DB021B
Operating Temperature (Case)
Com.
0°C to 70°C
Ind.
-40°C to 85°C
V
CC
Power Supply
(1)
2.7V to 3.6V
8.1 DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
SB
Standby Current
CS
, RESET, WP = V
CC
, all inputs
at CMOS levels
210µA
I
CC1
(1)
Active Current, Read
Operation
f = 15 MHz; I
OUT
= 0 mA;
V
CC
= 3.6V
410mA
I
CC2
Active Current,
Program/Erase Operation
V
CC
= 3.6V 15 35 mA
I
LI
Input Load Current V
IN
= CMOS levels 1 µA
I
LO
Output Leakage Current V
I/O
= CMOS levels 1 µA
V
IL
Input Low Voltage 0.6 V
V
IH
Input High Voltage 2.0 V
V
OL
Output Low Voltage I
OL
= 1.6 mA; V
CC
= 2.7V 0.4 V
V
OH
Output High Voltage I
OH
= -100 µA V
CC
- 0.2V V
14
1937J–DFLSH–9/05
AT45DB021B
8.3 Input Test Waveforms and Measurement Levels
t
R
, t
F
< 3 ns (10% to 90%)
8.4 Output Test Load
8.2 AC Characteristics
Symbol Parameter Min Max Units
f
SCK
SCK Frequency 20 MHz
f
CAR
SCK Frequency for Continuous Array Read 20 MHz
t
WH
SCK High Time 22 ns
t
WL
SCK Low Time 22 ns
t
CS
Minimum CS High Time 250 ns
t
CSS
CS Setup Time 250 ns
t
CSH
CS Hold Time 250 ns
t
CSB
CS High to RDY/BUSY Low 200 ns
t
SU
Data In Setup Time 5 ns
t
H
Data In Hold Time 10 ns
t
HO
Output Hold Time 0 ns
t
DIS
Output Disable Time 18 ns
t
V
Output Valid 20 ns
t
XFR
Page to Buffer Transfer/Compare Time 250 µs
t
EP
Page Erase and Programming Time 20 ms
t
P
Page Programming Time 14 ms
t
PE
Page Erase Time 8ms
t
BE
Block Erase Time 12 ms
t
RST
RESET Pulse Width 10 µs
t
REC
RESET Recovery Time 1 µs
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
2.0
0.8
2.4V
DEVICE
UNDER
TEST
30 pF
15
1937J–DFLSH–9/05
AT45DB021B
9. AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low
when CS
makes a high-to-low transition, and Waveform 2 shows the SCK signal being high
when CS
makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup
and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-
ing that is compatible with SPI Mode 3.
9.1 Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
9.2 Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
CS
SCK
SI
SO
t
CSS
VALID IN
t
H
t
SU
t
WH
t
WL
t
CSH
t
CS
t
V
HIGH IMPEDANCE
VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
CS
SCK
SI
SO
t
CSS
VALID IN
t
H
t
SU
t
WL
t
WH
t
CSH
t
CS
t
V
HIGH Z
VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE

AT45DB021B-SU

Mfr. #:
Manufacturer:
Description:
IC FLASH 2M SPI 20MHZ 8SOIC
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