CY28409
Document #: 38-07445 Rev. *D Page 10 of 17
PCI_STP# Assertion
[2]
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
SU
). (See
Figure 7.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Note:
2. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 7. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F
PCI
SRC 100MHz
Tsu
Tdrive_SRC
Figure 8. PCI_STP# Deassertion Waveform
CY28409
Document #: 38-07445 Rev. *D Page 11 of 17
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3 ms
Delay
State 0
State 2 State 3
Wait for
VTT_PWRGD#
Sample Sels
Off
Off
On
On
State 1
Device is not affected,
VTT_PWRGD# is ignored
Figure 9. VTT_PWRGD# Timing Diagram
VTT_PWRGD# = Low
Delay
>0.25 ms
S1
Power Off
S0
VDDA = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for <1.8 ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDDA = off
Figure 10. Clock Generator Power-up/Run State Diagram
CY28409
Document #: 38-07445 Rev. *D Page 12 of 17
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
V
DD
Core Supply Voltage –0.5 4.6 V
V
DD_A
Analog Supply Voltage –0.5 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 V
DD
+ 0.5 VDC
T
S
Temperature, Storage Non-functional –65 150 °C
T
A
Temperature, Operating Ambient Functional 0 70 °C
T
J
Temperature, Junction Functional 150 °C
Ø
JC
Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 15 °C/W
Ø
JA
Dissipation, Junction to Ambient JEDEC (JESD 51) 45 °C/W
ESD
HBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 V
UL–94 Flammability Rating @ 1/8 in. V–0
MSL Moisture Sensitivity Level 1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VDD_A
,
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
V
ILI2C
Input Low Voltage SDATA, SCLK 1.0 V
V
IHI2C
Input High Voltage SDATA, SCLK 2.2 V
V
IL
Input Low Voltage V
SS
– 0.5 0.8 V
V
IH
Input High Voltage 2.0 V
DD
+ 0.5 V
I
IL
Input Low Leakage Current except internal pull-ups resistors, 0 < V
IN
< V
DD
–5 µA
I
IH
Input High Leakage Current except internal pull-down resistors, 0 < V
IN
< V
DD
5 µA
V
OL
Output Low Voltage I
OL
= 1 mA 0.4 V
V
OH
Output High Voltage I
OH
= –1 mA 2.4 V
I
OZ
High-impedance Output Current –10 10 µA
I
DD
Dynamic Supply Current All outputs loaded per Table 9 and Figure 11 350 mA
C
IN
Input Pin Capacitance 2 5 pF
C
OUT
Output Pin Capacitance 3 6 pF
L
IN
Pin Inductance –7nH
V
XIH
Xin High Voltage 0.7V
DD
V
DD
V
V
XIL
Xin Low Voltage 0 0.3V
DD
V
I
PD3.3V
Power-down Supply Current PD# Asserted 1 mA
AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
Crystal
T
DC
XIN Duty Cycle The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
47.5 52.5 %
T
PERIOD
XIN Period When XIN is driven from an external clock
source
69.841 71.0 ns
T
R
/ T
F
XIN Rise and Fall Times Measured between 0.3V
DD
and 0.7V
DD
10.0 ns
T
CCJ
XIN Cycle to Cycle Jitter As an average over 1-µs duration 500 ps
L
ACC
Long-term Accuracy Over 150 ms 300 ppm

CY28409ZXCT

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Synthesizer / Jitter Cleaner System Clock for Intel Grantsdale, 865 and 875 chipsets (CK409)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet