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CY28409ZXCT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
CY28409
Document #: 38-07445 Rev. *D Page 4 of 17
Control Registers
20:27 Byte Count – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29:36 Data byte 1 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 2 – 8 bits 30:37 Byte count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge from master
.... ...................... 39:46 Data byte from slave – 8 bits
.... Data Byte (N–1) – 8 bits 47 Acknowledge from master
.... Acknowledge from slave 48:55 Data byte from slave – 8 bits
.... Data Byte N – 8 bits 56 Acknowledge from master
.... Acknowledge from slave .... Data byte N from slave – 8 bits
.... Stop .... Acknowledge from master
.... Stop
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
Table 5. Byte Read and Byte Write protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write = 0 9 Write = 0
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[4:0] of the
command code represents the offset of the byte to
be accessed
11:18 Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[4:0] of
the command code represents the offset of the
byte to be accessed
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Data byte from master – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29 Stop 28 Read = 1
29 Acknowledge from slave
30:37 Data byte from slave – 8 bits
38 Acknowledge from master
39 Stop
Byte 0:Control Register 0
Bit @Pup Name Description
7 0 Reserved Reserved, Set = 0
6 1 PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength
5 0 Reserved Reserved, Set = 0
4 0 Reserved Reserved, Set = 0
CY28409
Document #: 38-07445 Rev. *D Page 5 of 17
3 Externally
Selected
PCI_STP# PCI_STP# reflects the current value of the external PCI_STP# pin.
0 = PCI_STP# pin is LOW.
2 Externally
Selected
CPU_STP# CPU_STP# reflects the current value of the external CPU_STP# pin.
0 = CPU_STP# pin is LOW.
1 Externally
Selected
FS_B FS_B reflects the value of the FS_B pin sampled on power-up.
0 Externally
Selected
FS_A FS_A reflects the value of the FS_A pin sampled on power-up.
Byte 1: Control Register 1
Bit @Pup Name Description
7 0 SRCT, SRCC Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
6 1 SRCT, SRCC SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
5 1 Reserved Reserved, Set = 1
4 1 Reserved Reserved, Set = 1
3 1 Reserved Reserved, Set = 1
2 1 CPUT2, CPUC2 CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
1 1 CPUT1, CPUC1 CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
0 1 CPUT0, CPUC0 CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Byte 2: Control Register 2
Bit @Pup Name Description
7 0 SRCT, SRCC SRCT/C Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
6 0 SRCT, SRCC SRCT/C Stop Drive Mode
0 = Driven during PCI_STP, 1 = Three-state during PCI_STP
5 0 CPUT2, CPUC2 CPUT/C2 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
4 0 CPUT1, CPUC1 CPUT/C1 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
3 0 CPUT0, CPUC0 CPUT/C0 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
2 0 CPUT2, CPUC2 CPUT/C2 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
1 0 CPUT1, CPUC1 CPUT/C1 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
0 0 CPUT0, CPUC0 CPUT/C0 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 SW PCI STOP SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
6 1 PCI6 PCI6 Output Enable
0 = Disabled, 1 = Enabled
Byte 0:Control Register 0 (continued)
Bit @Pup Name Description
CY28409
Document #: 38-07445 Rev. *D Page 6 of 17
5 1 PCI5 PCI5 Output Enable
0 = Disabled, 1 = Enabled
4 1 PCI4 PCI4 Output Enable
0 = Disabled, 1 = Enabled
3 1 PCI3 PCI3 Output Enable
0 = Disabled, 1 = Enabled
2 1 PCI2 PCI2 Output Enable
0 = Disabled, 1 = Enabled
1 1 PCI1 PCI1 Output Enable
0 = Disabled, 1 = Enabled
0 1 PCI0 PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 USB_48 USB_48 Drive Strength
0 = High drive strength, 1 = Low drive strength
6 1 USB_48 USB_48 Output Enable
0 = Disabled, 1 = Enabled
5 0 PCIF2 Allow control of PCIF2 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
4 0 PCIF1 Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
3 0 PCIF0 Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
2 1 PCIF2 PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1 1 PCIF1 PCIF1 Output Enable
0 = Disabled, 1 = Enabled
0 1 PCIF0 PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register 5
Bit @Pup Name Description
7 1 DOT_48 DOT_48 Output Enable
0 = Disabled, 1 = Enabled
6 1 Reserved Reserved, Set = 1
5 0 3V66_4/VCH VCH Select 66-MHz/48-MHz
0 = 3V66 mode, 1 = VCH (48-MHz) mode
4 1 3V66_4/VCH 3V66_4/VCH Output Enable
0 = Disabled, 1 = Enabled
3 1 3V66_3 3V66_3 Output Enable
0 = Disabled, 1 = Enabled
2 1 3V66_2 3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1 1 3V66_1 3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0 1 3V66_0 3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3 (continued)
Bit @Pup Name Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

CY28409ZXCT

Mfr. #:
Buy CY28409ZXCT
Manufacturer:
Silicon Labs
Description:
Clock Synthesizer / Jitter Cleaner System Clock for Intel Grantsdale, 865 and 875 chipsets (CK409)
Lifecycle:
New from this manufacturer.
Delivery:
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