LTC1857/LTC1858/LTC1859
13
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For more information www.linear.com/LTC1857
APPLICATIONS INFORMATION
Figure 5. LTC1859 Histogram for 4096 Conversions
11 1111 1111 1111 for the LTC1858 and between 0000
0000 0000 and 1111 1111 1111 for the LTC1857.
As mentioned earlier, the internal reference is factory
trimmed to 2.50V. To make sure that the reference buffer
gain is not compensating for trim errors in the reference,
REFCOMP is trimmed with an accurate external 2.5V refer
-
ence applied to V
REF
. For unipolar inputs, an input voltage
of FS – 1.5LSBs should be applied to the “+” input and the
appropriate reference adjusted until the output code flick
-
ers between 1111 1111 1111 1110 and 1111 1111 1111
1111 for the LTC1859, between 11 1111 1111 1110 and
11 1111 1111 1111 for the LTC1858 and between 1111
1111 1110 and 1111 1111 1111 for the LTC1857.
For bipolar inputs, an input voltage of FS – 1.5LSBs should
be applied to the “+” input and the appropriate reference
adjusted until the output code flickers between 0111 1111
1111 1110 and 0111 1111 1111 1111 for the LTC1859,
between 01 1111 1111 1110 and 01 1111 1111 1111 for
the LTC1858 and between 0111 1111 1110 and 0111 1111
1111 for the LTC1857.
These adjustments as well as the factory trims affect all
channels. The channel-to-channel offset and gain error
matching are guaranteed by design to meet the specifica
-
tions in the Converter Characteristics table.
DC PERFORMANCE
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where
a DC signal is applied to the input of the MUX and the
resulting output codes are collected over a large number
of conversions. For example in Figure 5 the distribution
of output code is shown for a DC input that has been
digitized 4096 times. The distribution is Gaussian and the
RMS code transition is about 1LSB for the LTC1859.
DIGITAL INTERFACE
Internal Clock
The ADC has an internal clock that is trimmed to achieve
a typical conversion time of 4µs. No external adjustments
are required and, with the maximum acquisition time of
4µs, throughput performance of 100ksps is assured.
3V Input/Output Compatible
The LTC1857/LTC1858/LTC1859 operate on a 5V supply,
which makes the devices easy to interface to 5V digital
systems. These devices can also interface to 3V digital
systems: the digital input pins (SCK, SDI, CONVST and
RD) of the LTC1857/LTC1858/LTC1859 recognize 3V or 5V
inputs. The LTC1857/LTC1858/LTC1859 have a dedicated
output supply pin (OVP) that controls the output swings
of the digital output pins (SDO, BUSY) and allows the part
to interface to either 3V or 5V digital systems. The output
is two’s complement binary for bipolar mode and offset
binary for unipolar mode.
Timing and Control
Conversion start and data read are controlled by two digital
inputs: CONVST and RD. To start a conversion and put
the sample-and-hold into the hold mode bring CONVST
high for no less than 40ns. Once initiated it cannot be re
-
started until the conversion is complete. Converter status
is indicated by the BUSY output and this is low while the
conversion is in progress.
Figures 6a and 6b show two different modes of opera
-
tion for the LTC1859. For the 12-bit LTC1857 and 14-bit
LTC1858, the last four and two bits of the SDO will output
zeros respectively. In mode 1 (Figure 6a), RD is tied low.
The rising edge of CONVST starts the conversion. The data
outputs are always enabled. The MSB of the data output
is available after the conversion. In mode 2 (Figure 6b),
CONVST and RD are tied together. The rising edge of the
CONVST signal starts the conversion. Data outputs are in
CODE
–4 –3
0
COUNT
200
600
800
1000
2 3
1800
1859 F05
400
–2
–1 0
1 4
1200
1400
1600
LTC1857/LTC1858/LTC1859
14
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Figure 6a. Mode 1 for the LTC1859*. CONVST Starts a Conversion, Data Output is Always Enabled (RD = 0)
Figure 6b. Mode 2 for the LTC1859*. CONVST and RD Tied Together. CONVST Starts a Conversion, Data is Read by RD
SGL/
DIFF
1
t
4
RD = 0
SCK
SDI
SDO
CONVST
BUSY
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0
UNI GAIN NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB)
B11 B10 B9 B8 B1 B0 (LSB)
t
ACQ
t
7
t
6
t
2
t
CONV
t
1
t
10
t
11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
1 2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0
UNI GAIN NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB)
B11 B10 B9 B8 B1
1859 F06a
B0 (LSB)
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t
5
t
3
t
12
t
12
SGL/
DIFF
1
t
4
CONVST = RD
SCK
SDI
Hi-Z
SDO
BUSY
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0
UNI GAIN NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB)
B11 B10 B9 B8 B1 B0 (LSB)
t
ACQ
t
13
t
2
t
CONV
Hi-Z
t
10
t
11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
1 2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0
UNI GAIN NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB)
B11 B10 B9 B8 B1
1859 F06b
B0 (LSB)
Hi-Z
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t
5
t
3
t
9
t
8
t
7
t
6
Figure 7. Operating Sequence for the LTC1859*
SGL/
DIFF
1
t
4
RD
SCK
SDI
Hi-Z
SDO
BUSY
CONVST
2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0
UNI GAIN NAP SLEEP DON’T CARE
DON’T
CARE
B14 B13 B12B15 (MSB)
B11 B10 B9 B8 B1 B0 (LSB)
t
ACQ
t
13
t
2
t
1
t
CONV
Hi-Z
t
10
t
11
SHIFT CONFIGURATION WORD IN
SGL/
DIFF
1 2 3 4 5 6 7 8 15 16
ODD/
SIGN
SELECT
1
SELECT
0
UNI GAIN NAP SLEEP DON’T CARE
B14 B13 B12B15 (MSB)
B11 B10 B9 B8 B1
1859 F07
B0 (LSB)
Hi-Z
SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN
t
5
t
3
t
9
t
8
t
7
t
6
*For the 12-bit LTC1857 and 14-bit LTC1858, the last four and two bits of the SDO will output zeros respectively.
APPLICATIONS INFORMATION
LTC1857/LTC1858/LTC1859
15
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For more information www.linear.com/LTC1857
0
1
2
3
4
5
6
7
CHANNEL
COM (
)
8 Single-Ended
+
+
+
+
+
+
+
0,1
CHANNEL
4 Differential
2,3
4,5
6,7
+ (
)
+
+
(
)
+ (
)
+ (
)
(
+
)
(
+
)
(
+
)
(
+
)
4
5
6
7
CHANNEL
COM (
)
Combinations of
Differential and Single-Ended
+
+
+
+
+
+
0,1
2,3
COM (UNUSED)
Changing the
MUX Assignment “On the Fly”
COM (
)
4,5
6,7
4,5
1ST CONVERSION 2ND CONVERSION
+
+
+
+
+
7
6
{
{
{
{
{
{
{
{
{
1859 F08
APPLICATIONS INFORMATION
three-state at this time. When the conversion is complete
(BUSY goes high), CONVST and RD go low to enable the
data output for the previous conversion.
SERIAL DATA INPUT (SDI) INTERFACE
The
LTC1857/LTC1858/LTC1859
communicate with micro-
processors and other external circuitry via a synchronous,
full duplex, 3-wire serial interface (see Figure 7). The shift
clock (SCK) synchronizes the data transfer with each bit
being transmitted on the falling SCK edge and captured
on the rising SCK edge in both transmitting and receiving
systems. The data is transmitted and received simultane
-
ously (full duplex).
An 8-bit input word is shifted into the SDI input which
configures the LTC1857/LTC1858/LTC1859 for the next
conversion. Simultaneously, the result of the previous
conversion is output on the SDO line. At the end of the
data exchange the requested conversion begins by ap
-
plying a rising edge on CONVST. After t
CONV
, the conver-
sion is complete and the results will be available on the
next data transfer cycle. As shown below, the result of a
conversion is delayed by one conversion from the input
word requesting it.
SGL/
DIFF
SELECT
1
SELECT
0
UNI GAIN NAP
MUX ADDRESS
INPUT RANGE
POWER DOWN
SELECTION
1859 AI02
ODD
SIGN
SLEEP
SDI
SDO SDO
WORD 0
SDI
WORD 1
DATA
TRANSFER
SDO
WORD 2
SDI
WORD 3
SDO
WORD 1
SDI
WORD 2
DATA
TRANSFER
t
CONV
A/D
CONVERSION
t
CONV
A/D
CONVERSION
1859 • AI01
Figure 8. Examples of Multiplexer Options on the LTC1857/LTC1858/LTC1859
INPUT DATA WORD
The LTC1857/LTC1858/LTC1859 8-bit data word is clocked
into the SDI input on the first eight rising SCK edges. Fur
-
ther inputs on the SDI pin are then ignored until the next
conversion. The eight bits of the input word are defined
as follows:
Table 1. Multiplexer Channel Selection
MUX ADDRESS DIFFERENTIAL CHANNEL SELECTION MUX ADDRESS SINGLE-ENDED CHANNEL SELECTION
SGL/
DIFF
ODD
SIGN
SELECT
1 0
0 1 2 3 4 5 6 7
SGL/
DIFF
ODD
SIGN
SELECT
1 0
0 1 2 3 4 5 6 7 COM
0 0 0 0 + 1 0 0 0 +
0 0 0 1 + 1 0 0 1 +
0 0 1 0 + 1 0 1 0 +
0 0 1 1 + 1 0 1 1 +
0 1 0 0 + 1 1 0 0 +
0 1 0 1 + 1 1 0 1 +
0 1 1 0 + 1 1 1 0 +
0 1 1 1 + 1 1 1 1 +

LTC1857IG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 8-Ch, 12-B, 100ksps SoftSpan A/D Convs w
Lifecycle:
New from this manufacturer.
Delivery:
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