LTC1857/LTC1858/LTC1859
5
185789fb
For more information www.linear.com/LTC1857
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency Through CH0 to CH7 Inputs
Through ADC
+
, ADC
–
Only
l
100
166
kHz
kHz
t
CONV
Conversion Time
l
4 5 µs
t
ACQ
Acquisition Time Through CH0 to CH7 Inputs
Through ADC
+
, ADC
–
Only
l
1
4 µs
µs
f
SCK
SCK Frequency (Note 14)
l
0 20 MHz
t
r
SDO Rise Time See Test Circuits 6 ns
t
f
SDO Fall Time See Test Circuits 6 ns
t
1
CONVST High Time
l
40 ns
t
2
CONVST to BUSY Delay C
L
= 25pF, See Test Circuits
l
15 30 ns
t
3
SCK Period
l
50 ns
t
4
SCK High
l
10 ns
t
5
SCK Low
l
10 ns
t
6
Delay Time, SCK↓ to SDO Valid
C
L
= 25pF, See Test Circuits
l
25 45 ns
t
7
Time from Previous SDO Data Remains
Valid After SCK↓
C
L
= 25pF, See Test Circuits
l
5 20 ns
t
8
SDO Valid After RD↓
C
L
= 25pF, See Test Circuits
l
11 30 ns
t
9
RD↓ to SCK Setup Time
l
20 ns
t
10
SDI Setup Time Before SCK↑
l
0 ns
t
11
SDI Hold Time After SCK↑
l
7 ns
t
12
SDO Valid Before BUSY↑
RD = Low, C
L
= 25pF, See Test Circuits
l
5 20 ns
t
13
Bus Relinquish Time See Test Circuits
l
10 30 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AV
DD
=
DV
DD
= OV
DD
= V
DD
, they will be clamped by internal diodes. This product
can handle currents of greater than 100mA below ground or above V
DD
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to V
DD
.
Note 5: V
DD
= 5V, f
SAMPLE
= 100kHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended analog MUX input with respect to ground or ADC
+
with respect to
ADC
–
tied to ground.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and
1111 1111 1111 for the LTC1857. Unipolar zero error is the offset voltage
measured from 0.5LSB when the output codes flicker between 0000 0000
0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000
0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000
0000 0000 and 0000 0000 0001 for the LTC1857.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error. For unipolar
full-scale error, the deviation of the last code transition from ideal, divided
by the full-scale range, and includes the effect of offset error.
Note 12: All Specifications in dB are referred to a full-scale ±10V input.
Note 13: Recovers to specified performance after (2 • FS) input
overvoltage.
Note 14: t
6
of 45ns maximum allows f
SCK
up to 10MHz for rising capture
with 50% duty cycle and f
SCK
up to 20MHz for falling capture (with 5ns
setup time for the receiving logic).
Note 15: The specification is referred to the ±10V input range.
