ISPLSI 1024EA-200LT100 Datasheet ISPLSI 1024EA-100LT100, ISPLSI 1024EA-125LT100, ISPLSI 1024EA-200LT100 | P1-P3

ispLSI

1024EA

In-System Programmable High Density PLD

1024ea_02 1

USE ispMACH 4A5 FOR NEW

5V DESIGNS

Functional Block DiagramFeatures

• HIGH DENSITY PROGRAMMABLE LOGIC

— 4000 PLD Gates

— 48 I/O Pins, Two Dedicated Inputs

— 144 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• NEW FEATURES

— 100% IEEE 1149.1 Boundary Scan Testable

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems (V

CCIO Pin)

— Open-Drain Output Option

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

— fmax = 200 MHz Maximum Operating Frequency

—

tpd = 4.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

Output Routing Pool

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

CLK

Global Routing Pool (GRP)

0139/1024EA

Logic

Array

GLB

Description

The ispLSI 1024EA is a High Density Programmable

Logic Device containing 144 Registers, 48 Universal I/O

pins, two Dedicated Input pins, four Dedicated Clock

Input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 1024EA features 5V in-system

diagnostic capabilities via IEEE 1149.1 Test Access Port.

The ispLSI 1024EA device offers non-volatile

reprogrammability of the logic, as well as the intercon-

nects to provide truly reconfigurable systems. A functional

superset of the ispLSI 1024 architecture, the ispLSI

1024EA device adds user selectable 3.3V or 5V I/O and

open-drain output options.

The basic unit of logic on the ispLSI 1024EA device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…D7 (Figure 1). There are a total of 24 GLBs in the

ispLSI 1024EA device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinato-

rial or registered. Inputs to the GLB come from the GRP

and dedicated inputs. All of the GLB outputs are brought

back into the GRP so that they can be connected to the

inputs of any other GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. January 2002

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications ispLSI 1024EA

USE ispMACH 4A5 FOR NEW

5V DESIGNS

Functional Block Diagram

Figure 1. ispLSI 1024EA Functional Block Diagram

The device also has 48 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

programmed to be a combinatorial input, registered in-

put, latched input, output or bi-directional

I/O pin with 3-state control. The signal levels are TTL

compatible voltages and the output drivers can source 4

mA or sink 8 mA. Each output can be programmed

independently for fast or slow output slew rate to mini-

mize overall output switching noise. By connecting the

VCCIO pin to a common 5V or 3.3V power supply, I/O

output levels can be matched to 5V or 3.3V-compatible

voltages.

Eight GLBs, 16 I/O cells, dedicated inputs (if available)

and one ORP are connected together to make a

Megablock (Figure 1). The outputs of the eight GLBs are

connected to a set of 16 universal I/O cells by the ORP.

Each ispLSI 1024EA device contains three Megablocks.

The GRP has, as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 1024EA device are selected using

the Clock Distribution Network. Four dedicated clock pins

(Y0, Y1, Y2 and Y3) are brought into the distribution

network, and five clock outputs (CLK 0, CLK 1, CLK 2,

IOCLK 0 and IOCLK 1) are provided to route clocks to the

GLBs and I/O cells. The Clock Distribution Network can

also be driven from a special clock GLB (C0 on the ispLSI

1024EA device). The logic of this GLB allows the user to

create an internal clock from a combination of internal

signals within the device.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 1024EA are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration when the

device is in bulk erased state is totem-pole configuration.

The open-drain/totem-pole option is selectable through

the Lattice software tools.

RESET

Global

Routing

Pool

(GRP)

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

Clock

Distribution

Network

Generic

Logic Blocks

(GLBs)

Megablock

Output Routing Pool (ORP)

Input Bus

VCCIO

lnput Bus

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

I/O 35

I/O 34

I/O 33

I/O 32

I/O 0

I/O 1

I/O 2

I/O 3

I/O 12

I/O 13

I/O 14

I/O 15

TDI

TDO

TMS

TCK

I/O 8

I/O 9

I/O 10

I/O 11

I/O 4

I/O 5

I/O 6

I/O 7

I/O 47

I/O 46

I/O 45

I/O 44

GOE 1/IN 5

GOE 0/IN 4

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

B0 B1 B2 B3 B4 B5 B6 B7

0139B/1024EA

Specifications ispLSI 1024EA

USE ispMACH 4A5 FOR NEW

5V DESIGNS

Symbol Parameter Min Max Units

btcp

TCK [BSCAN test] clock pulse width 100 – ns

btch

TCK [BSCAN test] pulse width high 50 – ns

btcl

TCK [BSCAN test] pulse width low 50 – ns

btsu

TCK [BSCAN test] setup time 20 – ns

bth

TCK [BSCAN test] hold time 25 – ns

TCK [BSCAN test] rise and fall time 50 – mV/ns

btco

TAP controller falling edge of clock to valid output – 25 ns

btoz

TAP controller falling edge of clock to data output disable – 25 ns

btvo

TAP controller falling edge of clock to data output enable – 25 ns

btcpsu

BSCAN test Capture register setup time 40 – ns

btcph

BSCAN test Capture register hold time 25 – ns

btuco

BSCAN test Update reg, falling edge of clock to valid output – 50 ns

btuoz

BSCAN test Update reg, falling edge of clock to output disable – 50 ns

btuov

BSCAN test Update reg, falling edge of clock to output enable – 50 ns

Figure 2. Boundary Scan Waveforms and Timing Specifications

TMS

TDI

TCK

TDO

Data to be

captured

Data to be

driven out

Valid Data Valid Data

Data Captured

btsu

bth

btcl

btch

btcp

btvo

btco

btoz

btcpsu

btcph

btuov

btuco

btuoz

Boundary Scan

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

ISPLSI 1024EA-200LT100

Mfr. #:

Buy ISPLSI 1024EA-200LT100

Manufacturer:

Lattice

Description:

IC CPLD 64MC 4.5NS 100TQFP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ISPLSI 1024EA-200LT100

ISPLSI 1024EA-200LT100

Products related to this Datasheet