ISPLSI 1024EA-200LT100

10
Specifications ispLSI 1024EA
USE ispMACH 4A5 FOR NEW
5V DESIGNS
Maximum GRP Delay vs GLB Loads
GLB Load
ispLSI 1024EA-200
ispLSI 1024EA-125
ispLSI 1024EA-100
3
4
1 8 16 24
GRP Delay (ns)
4
2
GRP/GLB/1024EA
1
Power Consumption
Power consumption in the ispLSI 1024EA device de-
pends on two primary factors: the speed at which the
device is operating, and the number of product terms
used. Figure 4 shows the relationship between power
and operating speed.
0127/1024EA
Icc can be estimated for the ispLSI 1024EA using the following equation:
Icc = 17mA + (# of PTs * .726) + (# of nets * Max Freq * .0043)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
fmax (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
160
140
120
100
200
0
50 100 150 200
250
I
CC (mA)
220
ispLSI 1024EA
180
240
260
Figure 4. Typical Device Power Consumption vs fmax
11
Specifications ispLSI 1024EA
USE ispMACH 4A5 FOR NEW
5V DESIGNS
Pin Description
Input - Controls the operation of the ISP state machine.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB on the device.
Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on
the device.
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
NAME
Table 2-0002A/1024EA
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
Y1
Y0
TMS
Ground (GND)
GND
GOE 0/IN 4
1
GOE 1/IN 5
1
Input - Functions as an input pin to load programming data into the device and also used as one of
the two control pins for the ispJTAG state machine.
TDI
TDO
Output - Functions as an output pin to read serial shift register data.
TCK
Input - Functions as a clock pin for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
RESET
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB and/or any I/O cell on the device.
Y2
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any I/O cell on the device.
Y3
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signals, Vcc or GND.
TQFP PIN
NUMBERS
Vcc
VCC
2,
25,
39,
52,
75,
88,
20,
28,
32,
43,
47,
55,
70,
78,
82,
93,
97,
5,
15,
62,
11,
66,
12,
26,
49,
63,
76,
99,
21,
29,
33,
44,
48,
56,
71,
79,
83,
94,
98,
6,
36,
89,
40,
85,
13,
27,
50,
64,
77,
100
22,
30,
34,
45,
53,
57,
72,
80,
84,
95,
3,
7
37,
90
41,
86
NC
2
No Connect
Supply voltage for output drivers, 5V or 3.3V.
VCCIO
1,
24,
38,
51,
74,
87,
19,
23,
31,
42,
46,
54,
69,
73,
81,
92,
96,
4,
67
9
68
8
91
18
35
58
17
60
59
14,
61,
10,
65,
16
12
Specifications ispLSI 1024EA
USE ispMACH 4A5 FOR NEW
5V DESIGNS
2
NC
2
NC
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
1
GOE 1/IN 5
Y0
VCC
VCC
2
NC
2
NC
GND
GND
VCCIO
RESET
TDI
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
2
NC
2
NC
NC
2
NC
2
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
TMS
Y1
VCC
VCC
NC
2
NC
2
GND
GND
Y2
Y3
TCK
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
NC
2
NC
2
NC
2
NC
2
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
GOE 0/IN 4
1
GND
GND
NC
2
NC
2
VCC
VCC
I/O 35
I/O 34
I/O 33
I/O 32
I/O 31
I/O 30
I/O 29
NC
2
NC
2
2
NC
2
NC
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
TDO
GND
GND
2
NC
2
NC
VCC
VCC
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
2
NC
2
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
58
ispLSI 1024EA
Top View
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signal, VCC or GND.
100-TQFP/1024EA
ispLSI 1024EA 100-Pin TQFP Pinout Diagram
Pin Configurations

ISPLSI 1024EA-200LT100

Mfr. #:
Manufacturer:
Lattice
Description:
IC CPLD 64MC 4.5NS 100TQFP
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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