ISPLSI 1024EA-200LT100 Datasheet ISPLSI 1024EA-100LT100, ISPLSI 1024EA-125LT100, ISPLSI 1024EA-200LT100 | P4-P6

4

Specifications ispLSI 1024EA

USE ispMACH 4A5 FOR NEW

5V DESIGNS

Absolute Maximum Ratings

1

Supply Voltage V

cc

.................................. -0.5 to +7.0V

Input Voltage Applied........................ -2.5 to V

CC

+1.0V

Off-State Output Voltage Applied ..... -2.5 to V

CC

+1.0V

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (T

J

) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

T

A

= 0°C to + 70°C

SYMBOL

Table 2-0005/1024EA

VCC

VCCIO

VIH

VIL

PARAMETER

Supply Voltage

Supply Voltage: Output Drivers

Input High Voltage

Input Low Voltage

MIN. MAX. UNITS

4.75

3.0

2.0

0

5.25

3.6

V

cc

+1

0.8

V

Commercial

5V

3.3V

Capacitance (T

A

=25

o

C, f=1.0 MHz)

Erase/Reprogram Specifications

Table 2-0008/1024EA

PARAMETER

Erase/Reprogram Cycles

MINIMUM MAXIMUM UNITS

10000 — Cycles

C

SYMBOL

Table 2-0006/1024EA

C

PARAMETER

Y0 Clock Capacitance

10

UNITSTYPICAL TEST CONDITIONS

1

2

8Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance

(Commercial/Industrial)

pf

V = 5.0V, V = 2.0V

CC

CC PIN

5

Specifications ispLSI 1024EA

USE ispMACH 4A5 FOR NEW

5V DESIGNS

Output Load Conditions (see Figure 3)

Switching Test Conditions

TEST CONDITION R1 R2 CL

A 470Ω 390Ω 35pF

B

∞ 390Ω 35pF

470Ω 390Ω 35pF

Active High

Active Low

C

470Ω 390Ω 5pF

∞ 390Ω 5pF

Active Low to Z

at V +0.5V

OL

Active High to Z

at V -0.5V

OH

Table 2-0004/1024EA

Figure 3. Test Load

+ 5V

R

1

R

2

C

L

*

Device

Output

Test

Point

*C

L

includes Test Fixture and Probe Capacitance.

0213a

DC Electrical Characteristics

Over Recommended Operating Conditions

Input Pulse Levels

Table 2-0003/1024EA

Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

1.5V

See Figure 3

3-state levels are measured 0.5V from

steady-state active level.

1.5ns

V

OL

SYMBOL

1. One output at a time for a maximum duration of one second. V

OUT

= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using eight 16-bit counters.

3. Typical values are at V

CC

= 5V and T

A

= 25°C.

4. Unused inputs held at 0.0V.

5. Maximum I

CC

varies widely with specific device configuration and operating frequency. Refer to the

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor

Data Book CD-ROM to estimate maximum I

CC

.

Table 2-0007/1024EA

I

IH

I

IL

PARAMETER

I

IL-PU

I

OS

1

I

CC

2, 4, 5

Output Low Voltage

Input or I/O Low Leakage Current

Operating Power Supply Current

I

OL

= 8 mA

0V ≤ V

IN

≤ V

IL

(Max.)

V

IL

= 0.0V, V

IH

= 3.0V

CONDITION MIN. TYP.

3

MAX. UNITS

—

0.4

10

-10

10

V

OH

Output High Voltage

I

OH

= -2 mA, V

CCIO

= 3.0V

I

OH

= -4 mA, V

CCIO

= 4.75V

2.4 — — V

μA

Input or I/O High Leakage Current

V

CCIO

≤ V

IN

≤ 5.25V

(V

CCIO

- 0.2)V ≤ V

IN

≤ V

CCIO

μA

I/O Active Pull-Up Current

0V ≤ V

IN

≤ V

IL

—

-200

μA

Output Short Circuit Current V

CCIO

= 5.0V or 3.3V, V

OUT

= 0.5V — — -240 mA

— 152 mA—

f

TOGGLE

= 1 MHz

6

Specifications ispLSI 1024EA

USE ispMACH 4A5 FOR NEW

5V DESIGNS

t

pd1

UNITS

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

Table 2-0030A/1024EA

v.2.5

1

4

3

1

tsu2 + tco1

( )

DESCRIPTION#

2

PARAMETER

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass ns

t

pd2

A 2 Data Propagation Delay, Worst Case Path ns

f

max (Int.)

A 3 Clock Frequency with Internal Feedback MHz

f

max (Ext.)

— 4 Clock Frequency with External Feedback MHz

f

max (Tog.)

— 5 Clock Frequency, Max. Toggle MHz

t

su1

— 6 GLB Reg. Setup Time before Clock,4 PT Bypass ns

t

co1

A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns

t

h1

— 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns

t

su2

— 9 GLB Reg. Setup Time before Clock ns

t

co2

— 10 GLB Reg. Clock to Output Delay ns

t

h2

— 11 GLB Reg. Hold Time after Clock ns

t

r1

A 12 Ext. Reset Pin to Output Delay ns

t

rw1

— 13 Ext. Reset Pulse Duration ns

t

ptoeen

B 14 Input to Output Enable ns

t

ptoedis

C 15 Input to Output Disable ns

t

wh — 18 External Synchronous Clock Pulse Duration, High ns

t

wl

— 19 External Synchronous Clock Pulse Duration, Low ns

t

su3

— 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) ns

t

h3

— 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) ns

( )

1

twh + twl

t

goeen

B 16 Global OE Output Enable ns

t

goedis

C 17 Global OE Output Disable ns

-200

MIN. MAX.

— 4.5

—

200 —

—

2.0

—

143

250

3.0

0.0

3.5

0.0

3.5

3.0

0.0

6.0

3.5

4.0

5.5

7.0

—

— 4.5

-100

MIN. MAX.

— 10.0

—

100 —

—

4.0

—

77

125

6.0

0.0

7.0

0.0

6.5

3.5

0.0

12.5

6.0

7.0

13.5

15.0

—

— 9.0

-125

MIN. MAX.

— 7.5

—

125 —

—

3.0

—

100

167

4.5

0.0

5.5

0.0

5.0

3.0

0.0

10.0

4.5

5.5

10.0

12.0

—

— 7.0

External Timing Parameters

Over Recommended Operating Conditions

ISPLSI 1024EA-200LT100

ISPLSI 1024EA-200LT100

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