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ISPLSI 1024EA-200LT100

P1-P3P4-P6P7-P9P10-P12P13-P13
7
Specifications ispLSI 1024EA
USE ispMACH 4A5 FOR NEW
5V DESIGNS
Internal Timing Parameters
1
GRP Delay, 24 GLB Loads
tiobp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1024EA
v.2.5
Inputs
UNITSDESCRIPTION#
2
PARAM.
22 I/O Register Bypass ns
tiolat
23 I/O Latch Delay ns
tgrp24
33 ns
GLB
t1ptxor
36 1 ProductTerm/XOR Path Delay ns
t20ptxor
37 20 Product Term/XOR Path Delay ns
txoradj
38 XOR Adjacent Path Delay ns
tgbp
39 GLB Register Bypass Delay
ns
tgsu
40 GLB Register Setup Time before Clock ns
tgh
41 GLB Register Hold Time after Clock ns
tgco
42 GLB Register Clock to Output Delay ns
3
tgro
43 GLB Register Reset to Output Delay ns
tptre
44 GLB Product Term Reset to Register Delay ns
tptoe
45 GLB Product Term Output Enable to I/O Cell Delay ns
tptck
46 GLB Product Term Clock Delay ns
ORP
GRP
t4ptbpc
34 4 ProductTerm Bypass Path Delay (Combinatorial) ns
t4ptbpr
35 4 Product Term Bypass Path Delay (Registered) ns
torp
48 ORP Delay ns
torpbp
49 ORP Bypass Delay ns
tiosu
24 I/O Register Setup Time before Clock ns
tioh
25 I/O Register Hold Time after Clock ns
tioco
26 I/O Register Clock to Out Delay ns
tior
27 I/O Register Reset to Out Delay ns
tdin
28 Dedicated Input Delay ns
tgrp16
32 GRP Delay, 16 GLB Loads ns
tgrp8
31 GRP Delay, 8 GLB Loads ns
tgrp4
30 GRP Delay, 4 GLB Loads ns
tgrp1
29 GRP Delay, 1 GLB Load ns
tgfb
47 GLB Feedback Delay ns
MIN. MAX.
-200
—
—
—
—
—
—
—
—
—
—
—
—
—
0.2
1.0
1.5
—
—
3.0
0.0
—
—
—
—
—
—
—
0.3
4.0
2.5
1.9
1.9
1.9
0.6
1.4
3.8
2.5
2.1
1.7
1.8
—
—
2.5
0.8
0.1
—
—
4.0
4.0
1.1
2.1
1.7
1.5
1.3
—
0.0
-100
MIN. MIN.MAX. MAX.
-125
—
—
—
—
—
—
—
—
—
—
—
—
—
1.4
4.0
3.5
—
—
3.4
0.0
—
—
—
—
—
—
—
0.3
4.0
2.9
3.6
3.6
3.6
1.2
1.4
4.9
3.8
5.7
3.4
3.1
—
—
3.9
1.3
0.2
—
—
4.6
4.6
1.9
2.5
2.1
1.9
1.7
—
—
—
—
—
—
—
—
—
—
—
—
—
0.3
3.5
2.8
—
—
3.0
0.0
—
—
—
—
—
—
—
0.4
4.0
3.3
4.3
4.3
4.3
2.1
1.7
5.0
4.5
7.2
4.9
3.8
—
—
4.7
—0.3— 0.3
1.4
0.4
—
—
5.0
5.0
2.2
2.9
2.5
2.3
2.1
8
Specifications ispLSI 1024EA
USE ispMACH 4A5 FOR NEW
5V DESIGNS
Internal Timing Parameters
1
tob
1. Internal Timing Parameters are not tested and are for reference only.
Table 2-0037A/1024EA
v.2.5
Outputs
UNITSDESCRIPTION#PARAM.
50 Output Buffer Delay ns
toen
52 I/O Cell OE to Output Enabled ns
tgy0
55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk) ns
Global Reset
Clocks
tgr
60 Global Reset to GLB and I/O Registers ns
todis
53 I/O Cell OE to Output Disabled ns
tgy1/2
56 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns
tgcp
57 Clock Delay, Clock GLB to Global GLB Clock Line ns
tioy2/3
58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line ns
tiocp
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line ns
tgoe
54 Global OE ns
tsl
51 Output Buffer Delay, Slew Limited Adder ns
MIN. MAX.
-200
—
—
0.9
—
0.9
0.8
0.0
0.8
—
—
0.9
3.1
0.9
0.0
3.1
0.9
1.8
0.0
1.4
5.0
-100
MIN. MIN.MAX. MAX.
-125
—
—
1.1
—
0.9
0.8
0.0
0.8
—
—
——
2.0
5.1
1.9
5.1
1.5
1.8
0.0
2.8
3.9
5.0
5.1
—
—
1.9
—
1.5
0.8
0.0
0.8
—
—
—
1.7
4.0
1.1
4.0
0.9
1.8
0.0
2.82.8
3.0
5.0
2.1
9
Specifications ispLSI 1024EA
USE ispMACH 4A5 FOR NEW
5V DESIGNS
ispLSI 1024EA Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
0491/1032EA
Feedback#47
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
Input
Register
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2,3
D
Q
GRP4
GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Reg Bypass
I/O CellORPGLBGRPI/O Cell
#23 - 27
#30
#35
#34 Comb 4 PT Bypass
#36 - 38
#56 - 59
#44 - 46
#55
#54
#48
#49
Reset
Ded. In
GOE 0,1
#28
#22
RST
#60
#60
#39
#40 - 43
#52, 53
#50, 51
GRP Loading
Delay
#29, 31 - 33
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
=
=
=
=
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
iobp +
t
grp4 +
t
ptck(min))
(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
(0.3 + 1.5 + 1.9) + (0.2) - (0.3 + 1.5 + 1.5)0.6
1.6
7.4
0.8
1.4
7.2
=
=
=
=
t
h Clock (max) + Reg h - Logic
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.5 + 2.5) + (1.0) - (0.3 + 1.5 + 1.9)
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#22 + #30 + #46) + (#42) + (#48 + #50)
(0.3 + 1.5 + 2.5) + (1.4) + (0.8 + 0.9)
Table 2-0042a/1024EA
v.2.5
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
=
=
=
=
t
su
Logic + Reg (setup) - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
gy0(min) +
t
gco +
t
gcp(min))
(#22 + #30 + #37) + (#40) - (#55 + #42 + #57)
(0.3 + 1.5 + 1.9) + (0.2) - (0.9 + 1.4 + 0.8)
=
=
=
=
t
h
Clock (max) + Reg (hold) - Logic
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#55 + #42 + #57) + (#41) - (#22 + #30 + #37)
(0.9 + 1.4 + 1.8) + (1.0) - (0.3 + 1.5 + 1.9)
=
=
=
=
t
co
Clock (max) + Reg (clock-to-out) + Output
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gco) + (
t
orp +
t
ob)
(#55 + #42 + #57) + (#42) + (#48 + #50)
(0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9)
1. Calculations are based upon timing specifications for the ispLSI 1024EA-200.
P1-P3P4-P6P7-P9P10-P12P13-P13

ISPLSI 1024EA-200LT100

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Manufacturer:
Lattice
Description:
IC CPLD 64MC 4.5NS 100TQFP
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