Data Sheet AD1836A
Rev. A | Page 11 of 24
FUNCTIONAL OVERVIEW
ADCs
There are four ADC channels in the AD1836A configured as
two independent stereo pairs. One stereo pair is the primary
ADC and has fully differential inputs. The second pair can be
programmed to operate in one of three possible input modes
(programmed via SPI ADC Control Register 3). The ADC
section may also operate at a sample rate of 96 kHz with only
the two primary channels active. The ADCs include an
on-board digital decimation filter with 120 dB stop-band
attenuation and linear phase response, operating at an over-
sampling ratio of 128 (for 4-channel 48 kHz operation) or 64
(for 2-channel 96 kHz operation).
The primary ADC pair should be driven from a differential
signal source for best performance. The input pins of the
primary ADC connect directly to the internal switched
capacitors. To isolate the external driving op amp from the
“glitches” caused by the internal switched capacitors, each input
pin should be isolated by using a series-connected external
100 Ω resistor together with a 1 nF capacitor connected from
each input to ground. This capacitor must be of high quality, for
example, ceramic NPO or polypropylene film.
The secondary input pair can operate in one of three modes:
• Direct differential inputs (driven the same way as the
primary ADC inputs described above).
• PGA mode with differential inputs. In this mode, the PGA
amplifier can be programmed using the SPI port to give an
input gain of 0 dB to 12 dB in steps of 3 dB. External
capacitors are used after the PGA to supply filtering for the
switched capacitor inputs.
• Single-ended MUX/PGA mode. In this mode, two single-
ended stereo inputs are provided that can be selected using
the SPI port. Input gain can be programmed from 0 dB to
12 dB in steps of 3 dB. External capacitors are used to
supply filtering for the switched capacitor inputs.
Peak level information for each ADC may be read from the SPI
port through Registers 12 to 15. The data is supplied as a 10-bit
word with a maximum range of 0 dB to –60 dB and a resolution
of 1 dB. The registers hold peak information until read; after
reading, the registers are reset so that new peak information can
be acquired. Refer to the register descriptions for the details on
this format.
A digital high-pass filter can be switched in line with the ADCs
under SPI control to remove residual dc offsets. It has a 1.3 Hz,
6 dB per octave cutoff at a 44.1 kHz sample rate. The cutoff
frequency will scale directly with sample frequency. Note that it
does not remove these offsets from the peak level measurement.
The voltage at the V
REF
pin, FILTR (~2.25 V), can be used to
bias external op amps that buffer the input signals. See the
Power Supply and Voltage Reference section.
DACs
The AD1836A has six DAC channels arranged as three
independent stereo pairs, with six fully differential analog
outputs for improved noise and distortion performance. Each
channel has its own independently programmable attenuator,
adjustable in 1024 linear steps. Digital inputs are supplied
through three serial data input pins (one for each stereo pair)
and a common frame (DLRCLK) and bit (DBCLK) clock.
Alternatively, one of the “packed data” modes may be used to
access all six channels on a single TDM data pin.
Each set of differential output pins sits at the dc level of V
REF
and swings ±1.4 V for a 0 dB digital input signal. A single op
amp third order external low-pass filter is recommended to
remove high frequency noise present on the output pins, as well
as to provide differential-to-single-ended conversion. Note that
the use of op amps with low slew rate or low bandwidth may
cause high frequency noise and tones to fold down into the audio
band; care should be exercised in selecting these components.
The voltage at the V
REF
pin, FILTR (~2.25 V), can be used to
bias the external op amps that buffer the output signals. See the
Power Supply and Voltage Reference section.
CLOCK SIGNALS
The master clock frequency can be selected for 256, 512, or 768
times the sample rate. The default at power-up is 256 × f
S
. For
operation at 96 kHz, the master clock frequency should stay at
the same absolute frequency. For example, if the AD1836A is
programmed in 256 × f
S
, 48 kHz mode, the frequency of the
master clock would be 256 × 48 kHz = 12.288 MHz. If the
AD1836A is then switched to 96 kHz operation (via writing to
the SPI port), the frequency of the master clock should remain
at 12.288 MHz (which is now 128 × f
S
).
The internal clock used in the AD1836A is 512 × f
S
(48 kHz
mode) or 256 × f
S
(96 kHz mode). A clock doubler is used to
generate this internal master clock from the external clock in
the 256 × f
S
and 768 × f
S
modes.
To maintain the highest performance possible, it is recom-
mended that the clock jitter of the master clock signal be
limited to less than 300 ps rms, measured using the edge-to-
edge technique. Even at these levels, extra noise or tones may
appear in the DAC outputs if the jitter spectrum contains large
spectral peaks. It is highly recommended that an independent
crystal oscillator generate the master clock. In addition, it is
especially important that the clock signal should not be passed
