AD1836AASZRL Datasheet AD1836AASZ, AD1836ACSZ, AD1836AASZRL | P19-P21

AD1836A Data Sheet

Rev. A | Page 18 of 24

Table 11. Pin Function Changes in AUX Mode

Pin Name (I

2

S/AUX Mode)

I

2

S Mode

AUX Mode

ASDATA1(O) I

2

S Data Out, Internal ADC1 TDM Data Out, to SHARC

ASDATA2(O)/DAUXDATA(O) I

2

S Data Out, Internal ADC2 AUX—I

2

S Data Out (to External DAC)

DSDATA1(I) I

2

S Data In, Internal DAC1 TDM Data In, from SHARC

DSDATA2(I)/AAUXDATA(I) I

2

S Data In, Internal DAC2 AUX—I

2

S Data In 1 (to External ADC)

DSDATA3(I)/AAUXDATA2(I) I

2

S Data In, Internal DAC3 AUX—I

2

S Data In 2 (to External ADC)

ALRCLK(O) LRCLK for Internal ADC1, ADC2 TDM Frame Sync Out, to SHARC

ABCLK(O) BCLK for Internal ADC1, ADC2 TDM BCKL Out, to SHARC

DLRCLK(I)/AUXLRCLK(I/O) LRCLK In/Out Internal DACs AUX LRCLK In/Out, Driven by External IRCLK from ADC (in slave mode).

In master mode, driven by internal MCLK/512.

DBCLK(I)/AUXBCLK(I/O) BCLK In/Out Internal DACs AUX BCLK In/Out, Driven by External BCLK from ADC (in slave mode).

In master mode, driven by internal MCLK/8.

AUXDATA1

ASDATA2/DAUXDATA

DATA TO EXT DAC

BCLK AND LRCLK FOR

EXT DAC COMES FROM

ADC BCLK, LRCLK.

MUST BE IN I

2

S MODE.

ADC

SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO

RESET INTERNAL ADC COUNTER

ASDATA1

AUXDATA

I

2

S FORMATTER

MUX

AUXLRCLK

2 AUX

CHANNELS

6-CH

DAC

6 MAIN

CHANNELS

DAC

SPORT

DSDATA1

DSDATA2

DSDATA3

LRCLK

BCLK

SPORT

SYNC

4 ADC

S

AUXBCLK

AUXLRCLK

AUXDATA2

I

2

S

DECODE

LRCLK

ABCLK

ASDATA1

ALRCLK

ABCLK

ASDATA1

DATA TO SHARC

INDICATES MUX POSITION FOR AUX-TDM MODE

MASTER/SLAVE MODE,

FROM ADC SPI PORT

FROM SHARC

FROM EXT A/D

DSDATA1

DSDATA2/AUXDATA1

DSDATA3/AUXDATA2

DLRCLK/AUXLRCLK

MCLK

TIMING GEN

LRCLK BCLK

DBCLK/AUXBCLK

MUX

AUXBCLK

MUX

I

2

S

Figure 12. Extended TDM Mode (Internal Flow Diagram)

Data Sheet AD1836A

Rev. A | Page 19 of 24

SPI CONTROL REGISTERS

Note that all control registers default to zero at power-up.

Table 12. Serial SPI Word Format

Register Address Read/Write Reserved Data Field

15:12 11 10 9:0

4 Bits

1 = Read

0 = Write

0

10 Bits

Table 13. Register Addresses and Functions

Register Address RD/WR Reserved Function

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bits 9:0

0 0 0 0 0 0 DAC Control 1

0 0 0 1 0 0 DAC Control 2

0 0 1 0 0 0 DAC1L Volume

0 0 1 1 0 0 DAC1R Volume

0 1 0 0 0 0 DAC2L Volume

0 1 0 1 0 0 DAC2R Volume

0 1 1 0 0 0 DAC3L Volume

0 1 1 1 0 0 DAC3R Volume

1 0 0 0 0 0 ADC1L—Peak Level (Read-Only)

1 0 0 1 0 0 ADC1R—Peak Level (Read-Only)

1 0 1 0 0 0 ADC2L—Peak Level (Read-Only)

1 0 1 1 0 0 ADC2R—Peak Level (Read-Only)

1 1 0 0 0 0 ADC Control 1

1 1 0 1 0 0 ADC Control 2

1 1 1 0 0 0 ADC Control 3

1 1 1 1 0 0 Reserved

Table 14. DAC Control Register 1

Packed Mode: Eight channels are “packed” in DSDATA1 serial input. Packed Mode 128: Refer to Figure 7. Packed Mode 256: Refer to Figure 8.

Address RD/WR Reserved Function

De-emphasis Serial Mode Data-Word

Width

Power-Down Interpolator

Mode

Reserved

15, 14, 13, 12 11 10 9, 8 7, 6, 5 4, 3 2 1 0

0000 0 0 00 = None

01 = 44.1 kHz

10 = 32.0 kHz

11 = 48.0 kHz

000 = I

2

S

001 = RJ

010 = DSP

011 = LJ

100 = Packed Mode 256

101 = Packed Mode 128

110 = Reserved

111 = Reserved

00 = 24 Bits

01 = 20 Bits

10 = 16 Bits

11 = Reserved

0 = Normal

1 = PWRDWN

0 = 8× (48 kHz)

1 = 4× (96 kHz)

0

AD1836A Data Sheet

Rev. A | Page 20 of 24

Table 15. DAC Control Register 2

Address

RD/WR

Reserved

DAC Mute

DAC3R DAC3L DAC2R DAC2L DAC1R DAC1L

15, 14, 13, 12 11 10, 9, 8, 7, 6 5 4 3 2 1 0

0001 0 00000 0 = On

1 = Mute

0 = On

1 = Mute

0 = On

1 = Mute

0 = On

1 = Mute

0 = On

1 = Mute

0 = On

1 = Mute

Table 16. DAC Volume Registers

Address

RD/WR

Reserved

Function

Volume

15, 14, 13, 12 11 10 9:0

0010: DAC1L

0011: DAC1R

0100: DAC2L

0101: DAC2R

0110: DAC3L

0111: DAC3R

0 0 0 to 1023 in 1024 Linear Steps

Table 17. ADC Control Register 1

Address

RD/WR

Reserved

Function

Filter Power-Down Sample Rate Left Gain Right Gain

15, 14, 13, 12 11 10, 9 8 7 6 5, 4, 3 2, 1, 0

1100 0 00 0 = DC

1 = High Pass

0 = Normal

1 = PWRDWN

0 = 48 kHz

1 = 96 kHz

000 = 0 dB

001 = 3 dB

010 = 6 dB

011 = 9 dB

100 = 12 dB

101 = Reserved

110 = Reserved

111 = Reserved

000 = 0 dB

001 = 3 dB

010 = 6 dB

011 = 9 dB

100 = 12 dB

101 = Reserved

110 = Reserved

111 = Reserved

Table 18. ADC Control Register 2

Packed Mode: Eight channels are “packed” in ASDATA1 serial output. Packed Mode 128: Refer to Figure 5. Packed Mode 256: Refer to Figure 6.

Packed Mode AUX: Refer to Figure 9 to Figure 11. Note that Packed AUX mode affects the entire chip, including the DAC serial mode.

Address

RD/WR

Reserved

Master/Slave

AUX Mode

SOUT Mode

Word Width

ADC Mute

ADC2R ADC2L ADC1R ADC1L

15, 14, 13, 12 11 10 9 8, 7, 6 5, 4 3 2 1 0

1101 0 0 0 = Slave

1 = Master

000 = I

2

S

001 = RJ

010 = DSP

011 = LJ

100 = Packed Mode 256

101 = Packed Mode 128

110 = Packed Mode AUX

00 = 24 Bits

01 = 20 Bits

10 = 16 Bits

11 = Reserved

0 = On

1 = Mute

0 = On

1 = Mute

0 = On

1 = Mute

0 = On

1 = Mute

AD1836AASZRL

AD1836AASZRL

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