AD7891ASZ-1 Datasheet AD7891BSZ-1, AD7891ASZ-2, AD7891APZ-1 | P10-P12

AD7891

–9–

REV. D

TERMINOLOGY

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f

/2), excluding dc.

The ratio is dependent upon the number of quantization levels

in the digitization process; the more levels, the smaller the quan-

tization noise. The theoretical signal-to-(noise +distortion) ratio

for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Therefore, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the

fundamental. For the AD7891, it is defined as

THD dB log

()

++++

22222

V VVVV

23456

where V

is the rms amplitude of the fundamental and V

, V

and V

are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms

value of the next largest component in the ADC output spectrum

(up to f

/2 and excluding dc) to the rms value of the fundamental.

Normally, the value of this specification is determined by the larg-

est harmonic in the spectrum, but for parts where the harmonics

are buried in the noise floor, it is a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa ± nfb, where

m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for

which neither m nor n are equal to zero. For example, the

second-order terms include (fa + fb) and (fa – fb), while the

third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and

(fa – 2fb).

The AD7891 is tested using the CCIF standard where two

input frequencies near the top end of the input bandwidth are

used. In this case, the second- and third-order terms are of

different significance. The second-order terms are usually dis-

tanced in frequency from the original sine waves while the third-

order terms are usually at a frequency close to the input

frequencies. As a result, the second- and-third order terms are

specified separately. The calculation of the intermodulation

distortion is as per the THD specification where it is the ratio of

the rms sum of the individual distortion products to the rms

amplitude of the fundamental expressed in dBs.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale 20 kHz (AD7891-1) or 100 kHz (AD7891-2) sine wave

signal to one input channel and determining how much that

signal is attenuated in each of the other channels. The figure

given is the worst case across all eight channels.

Relative Accuracy

Relative accuracy or endpoint nonlinearity is the maximum

deviation from a straight line passing through the endpoints of

the ADC transfer function.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7891-1, ⴞ10 V and ⴞ5 V;

AD7891-2, ⴞ2.5 V)

This is the deviation of the last code transition (01. . .110 to

01. . .111) from the ideal 4 ¥ REF IN – 3/2 LSB (AD7891-1

± 10 V range), 2 ¥ REF IN – 3/2 LSB (AD7891-1 ± 5V range),

or REF IN – 3/2 LSB (AD7891-2, ± 2.5 V range), after the

bipolar zero error has been adjusted out.

Positive Full-Scale Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V)

This is the deviation of the last code transition (11. . .110 to

11. . .111) from the ideal 2 ¥ REF IN – 3/2 LSB (0 V to 5 V

range), or REF IN – 3/2 LSB (0 V to 2.5 V range), after the

unipolar offset error has been adjusted out.

Bipolar Zero Error (AD7891-1, ⴞ10 V and ⴞ5 V; AD7891-2, ⴞ2.5 V)

This is the deviation of the midscale transition (all 0s to all 1s)

from the ideal AGND – 1/2 LSB.

Unipolar Offset Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V)

This is the deviation of the first code transition (00. . .000 to

00. . .001) from the ideal AGND + 1/2 LSB.

Negative Full-Scale Error (AD7891-1, ⴞ10 V and ⴞ5 V;

AD7891-2, ⴞ2.5 V)

This is the deviation of the first code transition (10. . .000 to

10. . .001) from the ideal –4 ¥ REF IN + 1/2 LSB (AD7891-1

±10 V range), –2 ¥ REF IN + 1/2 LSB (AD7891-1 ± 5V range),

or –REF IN + 1/2 LSB (AD7891-2, ± 2.5 V range), after bipolar

zero error has been adjusted out.

Track/Hold Acquisition Time

Track/hold acquisition time is the time required for the output of

the track/hold amplifier to reach its final value, within ± 1/2 LSB,

after the end of conversion (the point at which the track/hold

returns to track mode). It also applies to situations where a

change in the selected input channel takes place or where there

is a step input change on the input voltage applied to the selected

input of the AD7891. It means the user must wait for the

duration of the track/hold acquisition time after the end of

conversion or after a channel change/step input change to V

before starting another conversion, to ensure the part operates

to specification.

AD7891

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REV. D

INTERFACE INFORMATION

The AD7891 provides two interface options, a 12-bit parallel

interface and a high speed serial interface. The required inter-

face mode is selected via the MODE pin. The two interface

modes are discussed in the following sections.

Parallel Interface Mode

The parallel interface mode is selected by tying the MODE

input to a logic high. Figure 2 shows a timing diagram illustrating

the operational sequence of the AD7891 in parallel mode for a

hardware conversion start. The multiplexer address is written to

the AD7891 on the rising edge of the WR input. The on-chip

track/hold goes into hold mode on the rising edge of CONVST;

conversion is also initiated at this point. When the conversion is

complete, the end of conversion line (EOC) pulses low to indi-

cate that new data is available in the AD7891’s output register.

This EOC line can be used to drive an edge-triggered interrupt

of a microprocessor. CS and RD going low accesses the 12-bit

conversion result. In systems where the part is interfaced to a

gate array or ASIC, this EOC pulse can be applied to the CS

and RD inputs to latch data out of the AD7891 and into the

gate array or ASIC. This means the gate array or ASIC does not

need any conversion status recognition logic, and it also elimi-

nates the logic required in the gate array or ASIC to generate

the read signal for the AD7891.

CONV

VALID DATA

OUTPUT

VALID DATA

INPUT

CONVST (I)

EOC (O)

CS (O)

WR (I)

RD (I)

DB0 TO DB11

(I/O)

NOTE

I = INPUT

O = OUTPUT

Figure 2. Parallel Mode Timing Diagram

CONVERTER DETAILS

The AD7891 is an 8-channel, high speed, 12-bit data acquisi-

tion system. It provides the user with signal scaling, multiplexer,

track/hold, reference, ADC, and high speed parallel and serial

interface logic functions on a single chip. The signal condition-

ing on the AD7891-1 allows the part to accept analog input

ranges of ± 5V or ± 10 V when operating from a single supply.

The input circuitry on the AD7891-2 allows the part to handle

input signal ranges of 0 V to +2.5 V, 0 V to +5 V, and ±2.5 V

again while operating from a single 5 V supply. The part requires

a 2.5 V reference that can be provided from the part’s own internal

reference or from an external reference source.

Conversion is initiated on the AD7891 either by pulsing the

CONVST input or by writing a Logic 1 to the SWCONV bit of

the control register. When using the hardware CONVST input,

the on-chip track/hold goes from track to hold mode and the

conversion sequence is started on the rising edge of the CONVST

signal. When a software conversion start is initiated, an internal

pulse is generated, delaying the track/hold acquisition point and

the conversion start sequence until the pulse is timed out. This

internal pulse is initiated (goes from low to high) whenever a

write to the AD7891 control register takes place with a 1 in the

SWCONV bit. It then starts to discharge and the track/hold

cannot go into hold and conversion cannot be initiated until the

pulse signal goes low. The internal pulse duration is equal to the

track/hold acquisition time. This allows the user to obtain a

valid result after changing channels and initiating a conversion

in the same write operation.

The conversion clock for the part is internally generated and

conversion time for the AD7891 is 1.6 ms from the rising edge of

the hardware CONVST signal. The track/hold acquisition time

for the AD7891-1 is 600 ns, while the track/hold acquisition

time for the AD7891-2 is 400 ns. To obtain optimum perfor-

mance from the part, the data read operation should not occur

during the conversion or during the 100 ns prior to the next

conversion. This allows the AD7891-1 to operate at throughput

rates up to 454.5 kSPS and the AD7891-2 to operate at through-

put rates up to 500 kSPS in the parallel mode and achieve data

sheet specifications. In the serial mode, the maximum achievable

throughput rate for both the AD7891-1 and the AD7891-2 is

357 kSPS (assuming a 20 MHz serial clock).

All unused analog inputs should be tied to a voltage within the

nominal analog input range to avoid noise pickup. For mini-

mum power consumption, the unused analog inputs should be

tied to AGND.

AD7891

–11–

REV. D

Serial Interface Mode

The serial interface mode is selected by tying the MODE input

to a logic low. In this case, five of the data/control inputs of the

parallel mode assume serial interface functions.

The serial interface on the AD7891 is a 5-wire interface with

read and write capabilities, with data being read from the output

control register via the DATA IN line. The part operates in a

slave or external clocking mode and requires an externally applied

serial clock to the SCLK input to access data from the data

framing signals for the read (RFS) and write (TFS) operations.

The serial interface on the AD7891 is designed to allow the part

to be interfaced to systems that provide a serial clock that is

synchronized to the serial data, such as the 80C51, 87C51,

68HC11, and 68HC05, and most digital signal processors.

When using the AD7891 in serial mode, the data lines DB11 to

DB10 should be tied to logic low, and the CS, WR, and RD

inputs should be tied to logic high. Pins DB4 to DB0 can be

tied to either logic high or logic low but must not be left floating

because this condition could cause the AD7891 to draw

large amounts of current.

Read Operation

Figure 3 shows the timing diagram for reading from the AD7891

in serial mode. RFS goes low to access data from the AD7891.

The serial clock input does not have to be continuous. The serial

data can be accessed in a number of bytes. However, RFS must

remain low for the duration of the data transfer operation. Six-

teen bits of data are transmitted in serial mode with the data

FORMAT bit first, followed by the three address bits in the

control register, followed by the 12-bit conversion result starting

with the MSB. Serial data is clocked out of the device on the

rising edge of SCLK and is valid on the falling edge of SCLK.

At the end of the read operation, the DATA OUT line is three-

stated by a rising edge on either the SCLK or RFS inputs, which-

ever occurs first.

Write Operation

Figure 4 shows a write operation to the control register of the

AD7891. The TFS input goes low to indicate to the part that a

serial write is about to occur. The AD7891 control register

requires only six bits of data. These are loaded on the first six

clock cycles of the serial clock with data on all subsequent clock

cycles being ignored. Serial data to be written to the AD7891

must be valid on the falling edge of SCLK.

Simplifying the Serial Interface

To minimize the number of interconnect lines to the AD7891

in serial mode, the user can connect the RFS and TFS lines

of the AD7891 together and read and write from the part simul-

taneously. In this case, a new control register data line selecting

the input channel and providing a conversion start command

should be provided on the DATA IN line, while the part pro-

vides the result from the conversion just completed on the

DATA OUT line.

DATA OUT (O)

SCLK (I)

RFS (I)

18A

NOTE

I = INPUT

O = OUTPUT

FORMAT A2 A1 A0 DB11 DB10 DB0

THREE-STATE

Figure 3. Serial Mode Read Operation

DATA IN (I)

SCLK (I)

TFS (I)

NOTE

I = INPUT

FORMATA0A1A0

CONV STBY

DON'T

CARE

DON'T

CARE

Figure 4. Serial Mode Write Operation

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD7891ASZ-1

Mfr. #:

Buy AD7891ASZ-1

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC Bipolar Inpt SGL-Sup Parallel 8CH 12B

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AD7891ASZ-1

AD7891ASZ-1

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