AD7891ASZ-1 Datasheet AD7891BSZ-1, AD7891ASZ-2, AD7891APZ-1 | P16-P18

AD7891

–15–

REV. D

As in the 8X51 circuit in Figure 7, the way the 68HC11 is

informed that a conversion is completed is not shown in the

diagram. The EOC line can be used to inform the 68HC11

that a conversion is complete by using it as an interrupt signal.

The interrupt service routine reads in the result of the conver-

sion. If a software conversion start is used, the 68HC11 can

wait for 2.0 ms (AD7891-2) or 2.2 ms (AD7891-1) before read-

ing from the AD7891.

68HC11*

DATA OUT

AD7891*

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

DATA IN

RFS

TFS

PC7

PC6

SCK

MOSI

MOSO

Figure 8. AD7891 to 68HC11 Interface

AD7891 to ADSP-21xx Serial Interface

An interface between the AD7891 and the ADSP-21xx is shown

in Figure 9. In the interface shown, either SPORT0 or SPORT1

can be used to transfer data to the AD7891. When reading

from the part, the SPORT must be set up with a serial word

length of 16 bits. When writing to the AD7891, a serial word

length of 6 bits or more can be used. Other setups for the

serial interface on the ADSP-21xx internal SCLK use alternate

framing mode and active low framing signal. Normally, the

EOC line from the AD7891 would be connected to the IRQ2

line of the ADSP-21xx to interrupt the DSP at the end of a

conversion (not shown in diagram).

ADSP-21xx*

DATA OUT

AD7891*

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

DATA IN

RFS

TFS

RFS

TFS

SCLK

Figure 9. AD7891 to ADSP-21xx Serial Interface

AD7891 to DSP5600x Serial Interface

Figure 10 shows a serial interface between the AD7891 and the

DSP5600x series of DSPs. When reading from the AD7891, the

DSP5600x should be set up for 16-bit data transfers, MSB first,

normal mode synchronous operation, internally generated word

frame sync, and gated clock. When writing to the AD7891, 8-bit

or 16-bit data transfers can be used. The frame sync signal from

the DSP5600x must be inverted before being applied to the

RFS and TFS inputs of the AD7891, as shown in Figure 10.

To monitor the conversion time of the AD7891, a scheme such

as those outlined in previous interfaces with EOC can be used.

This can be implemented by connecting the EOC line directly

to the IRQA input of the DSP5600x.

DSP5600x*

DATA OUT

AD7891*

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

DATA IN

RFS

TFS

FST (SC2)

SCK

STD

SRD

Figure 10. AD7891 to DSP5600x Serial Interface

AD7891 to TMS320xxx Serial Interface

The AD7891 can be interfaced to the serial port of TMS320xxx

DSPs, as shown in Figure 11. External timing generation circuitry

is necessary to generate the serial clock and syncs necessary for

the interface.

TMS320xxx*

DATA OUT

AD7891*

*ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

DATA IN

RFS

TFS

FSX

CLKX

CLKR

FSR

TIMING

GENERATION

CIRCUITRY

Figure 11. AD7891 to TMS320xxx Serial Interface

AD7891

–16–

REV. D

PARALLEL INTERFACING

The parallel port on the AD7891 allows the device to be interfaced

to microprocessors or DSP processors as a memory mapped

or I/O mapped device. The CS and RD inputs are common to

all memory peripheral interfacing. Typical interfaces to different

processors are shown in Figures 12 to 15. In all the interfaces

shown, an external timer controls the CONVST input of the

AD7891 and the EOC output interrupts the host DSP.

AD7891 to ADSP-21xx

Figure 12 shows the AD7891 interfaced to the ADSP-21xx

series of DSPs as a memory mapped device. A single wait state

may be necessary to interface the AD7891 to the ADSP-21xx

depending on the clock speed of the DSP. This wait state can

be programmed via the data memory wait state control register

of the ADSP-21xx (please see the ADSP-2100 family Users

Manual for details). The following instruction reads data

from the AD7891.

MR = DM (ADC)

where ADC is the address of the AD7891.

DATA BUS

ADDRESS BUS

DB11 TO DB0

AD7891*

*ADDITIONAL PINS OMITTED FOR CLARITY

IRQ2

D23 TO D8

EOC

ADDR

DECODE

DMS

ADSP-21xx*

A13 TO A0

Figure 12. AD7891 to ADSP-21xx Parallel Interface

AD7891 to TMS32020, TMS320C25, and TMS320C5x

Parallel interfaces between the AD7891 and the TMS32020,

TMS320C25, and TMS320C5x family of DSPs are shown in

Figure 13. The memory mapped address chosen for the

AD7891 should be chosen to fall in the I/O memory space of

the DSPs.

TMS320C25

ONLY

DATA BUS

ADDRESS BUS

DB11 TO DB0

AD7891*

*ADDITIONAL PINS OMITTED FOR CLARITY

INTx

D23 TO D0

EOC

MSC

ADDR

DECODE

A15 TO A0

TMS32020/

TMS320C25/

TMS320C5x*

READY

R/W

STRB

Figure 13. AD7891 to TMS32020/TMS320C25/TMS320C5x

Parallel Interface

The parallel interface on the AD7891 is fast enough to interface

to the TMS32020 with no extra wait states. If high speed glue

logic, such as 74AS devices, are used to drive the WR and RD

lines when interfacing to the TMS320C25, then again no wait

states are necessary. However, if slower logic is used, data accesses

may be slowed sufficiently when reading from and writing to the

part to require the insertion of one wait state. In such a case,

this wait state can be generated using the single OR gate to

combine the CS and MSC signals to drive the READY line of

the TMS320C25, as shown in Figure 13. Extra wait states are

necessary when using the TMS320C5x at their fastest clock

speeds. Wait states can be programmed via the IOWSR and

CWSR registers (see the TMS320C5x User Guide for details).

Data is read from the ADC using the following instruction:

IN D, ADC

where D is the memory location where the data is to be stored,

and ADC is the I/O address of the AD7891.

AD7891 to TMS320C3x

Figure 14 shows a parallel interface between the AD7891 and

the TMS320C3x family of DSPs. The AD7891 is interfaced to

the expansion bus of the TMS320C3x. A single wait state is

required in this interface. This can be programmed using the

WTCNT bits of the expansion bus control register (see the

TMS320C3x Users Guide for details). Data from the AD7891

can be read using the following instruction:

LDI ARn Rx¥ ,

where ARn is an auxiliary register containing the lower 16 bits

of the address of the AD7891 in the TMS320C3x memory

space, and Rx is the register into which the ADC data is loaded.

EXPANSION DATA BUS

ADDRESS BUS

DB11 TO DB0

AD7891*

*ADDITIONAL PINS OMITTED FOR CLARITY

INTx

XD23 TO XD0

EOC

ADDR

DECODE

XA15 TO XA0

XR/W

IOSTRB

TMS320C3x*

Figure 14. AD7891 to TMS320C3x Parallel Interface

AD7891

–17–

REV. D

AD7891 to DSP5600x

Figure 15 shows a parallel interface between the AD7891 and

the DSP5600x series of DSPs. The AD7891 should be mapped

into the top 64 locations of Y data memory. If extra wait states

are needed in this interface, they can be programmed using the

Port A Bus control register (see the DSP5600x Users Manual

for details). Data can be read from the AD7891 using the fol-

lowing instruction:

MOVEO Y: ADC, X0

where ADC is the address in the DSP5600x address space to

which the AD7891 has been mapped.

DATA BUS

ADDRESS BUS

DB11 TO DB0

AD7891*

*ADDITIONAL PINS OMITTED FOR CLARITY

IRQ

D23 TO D0

EOC

ADDR

DECODE

A15 TO A0

X/Y

DSP56000/

DSP56002*

Figure 15. AD7891 to DSP5600x Parallel Interface

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the specified performance. The PCB on which the AD7891 is

mounted should be designed such that the analog and digital

sections are separated and confined to certain areas of the board.

This facilitates the use of ground planes that can be separated

easily. A minimum etch technique is generally best for ground

planes because it gives the best shielding. Digital and analog

ground planes should be joined at only one place. If the AD7891

is the only device requiring an AGND to DGND connection,

then the ground planes should be connected at the AGND and

DGND pins of the AD7891. If the AD7891 is in a system where

multiple devices require an AGND to DGND connection, the

connection should still be made at one point only, a star ground

point established as close as possible to the AD7891.

Digital lines running under the device should be avoided because

these couple noise onto the die. The analog ground plane should

be allowed to run under the AD7891 to avoid noise coupling.

The power supply lines of the AD7891 should use as large a

trace as possible to provide low impedance paths and reduce the

effects of glitches on the power supply line. Fast switching sig-

nals like clocks should be shielded with digital ground to avoid

radiating noise to other parts of the board and should never be

run near the analog inputs. Avoid crossover of digital and analog

signals. Traces on opposite sides of the board should run at right

angles to each other. This reduces the effects of feedthrough

through the board. A microstrip technique is by far the best

technique but is not always possible with a double-sided board.

In this technique, the component side of the board is dedicated

to ground plane while signal traces are placed on the solder side.

The AD7891 should have ample supply bypassing located as close

to the package as possible, ideally right up against the device.

One of the V

pins (Pin 10 of the PLCC package and Pin 4

on the MQFP package) mainly drives the analog circuitry on

the chip. This pin should be decoupled to the analog ground

plane with a 10 mF tantalum bead capacitor in parallel with a

0.1 mF capacitor. The other V

pin (Pin 19 on the PLCC

package and Pin 13 on the MQFP package) mainly drives

digital circuitry on the chip. This pin should be decoupled to the

digital ground plane with a 0.1 mF capacitor. The 0.1 mF

capacitors should have low effective series resistance (ESR) and

effective series inductance (ESI), such as the common ceramic

types or surface mount types, which provide a low impedance

path to ground at high frequencies to handle transient currents

due to internal logic switching. Figure 16 shows the

recommended decoupling scheme.

(PIN 10, PLCC

PIN 4, MQFP)

DGND

AD7891

AGND

(PIN 19, PLCC

PIN 13, MQFP)

10␮F

0.1␮F

Figure 16. Recommended Decoupling Scheme for

the AD7891

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD7891ASZ-1

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Description:

Analog to Digital Converters - ADC Bipolar Inpt SGL-Sup Parallel 8CH 12B

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AD7891ASZ-1

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