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AD7891ASZ-1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD7891
–6–
REV. D
PIN FUNCTION DESCRIPTIONS
PLCC MQFP
Pin No. Pin No. Mnemonic Description
1–528–43 V
INXA
, V
INXB
Analog Input Channels. The AD7891 contains eight pairs of analog input channels. Each
34–44 channel contains two input pins to allow a number of different input ranges to be used
with the AD7891. There are two possible input voltage ranges on the AD7891-1. The
± 5V input range is selected by connecting the input voltage to both V
INXA
and V
INXB
,
while the ± 10 V input range is selected by applying the input voltage to V
INXA
and con-
necting V
INXB
to AGND. The AD7891-2 has three possible input ranges. The 0 V to
2.5 V input range is selected by connecting the analog input voltage to both V
INXA
and V
INXB
; the
0V to 5 V input range is selected by applying the input voltage to V
INXA
and connecting
V
INXB
to AGND while the ± 2.5 V input range is selected by connecting the analog input
voltage to V
INXA
and connecting V
INXB
to REF IN (provided this REF IN voltage comes
from a low impedance source). The channel to be converted is selected by the A2, A1,
and A0 bits of the control register. In the parallel interface mode, these bits are available as
three data input lines (DB3 to DB5) in a parallel write operation. While in the serial inter-
face mode, these three bits are accessed via the DATA IN line in a serial write operation.
The multiplexer has guaranteed break-before-make operation.
10, 19 4, 13 V
DD
Positive Supply Voltage, 5 V ± 5%.
11, 33 5, 27 AGND Analog Ground. Ground reference for track/hold, comparator, and DAC.
20 14 DGND Digital Ground. Ground reference for digital circuitry.
644STANDBY Standby Mode Input. TTL compatible input used to put the device into the power
save or standby mode. The STANDBY input is high for normal operation and low for
standby operation.
93 REF OUT/REF IN Voltage Reference Output/Input. The part can either be used with its own internal refer-
ence or with an external reference source. The on-chip 2.5 V reference voltage is pro-
vided at this pin. When using this internal reference as the reference source for the
part, REF OUT should be decoupled to REF GND with a 0.1 mF disc ceramic capaci-
tor. The output impedance of the reference source is typically 2 kW. When using an
external reference source as the reference voltage for the part, the reference source
should be connected to this pin. This overdrives the internal reference and provides the
reference source for the part. The reference pin is buffered on-chip but must be able to
sink or source current through this 2 kW resistor to the output of the on-chip reference.
The nominal reference voltage for correct operation of the AD7891 is 2.5 V.
71 REF GND Reference Ground. Ground reference for the part’s on-chip reference buffer. The REF
OUT pin of the part should be decoupled with a 0.1 mF capacitor to this REF GND
pin. If the AD7891 is used with an external reference, the external reference should also
be decoupled to this pin. The REF GND pin should be connected to the AGND pin
or the system’s AGND plane.
30 24 CONVST Convert Start. Edge-triggered logic input. A low-to-high transition on this input puts
the track/hold into hold and initiates conversion. When changing channels on the part,
sufficient time should be given for multiplexer settling and track/hold acquisition between
the channel change and the rising edge of CONVST.
32 26 EOC End-of-Conversion. Active low logic output indicating converter status. The end of con-
version is signified by a low-going pulse on this line. The duration of this EOC pulse is
nominally 80 ns.
12 6 MODE Interface Mode. Control input that determines the interface mode for the part. With this
pin at a logic low, the AD7891 is in its serial interface mode; with this pin at a logic high,
the device is in its parallel interface mode.
AD7891
–7–
REV. D
PARALLEL INTERFACE MODE FUNCTIONS
PLCC Pin No. MQFP Pin No. Mnemonic Description
8, 31 2, 25 NC No Connect. The two NC pins on the device can be left unconnected. If they
are to be connected to a voltage, it should be to ground potential. To ensure
correct operation of the AD7891, neither of the NC pins should be connected
to a logic high potential.
29 23 CS Chip Select Input. Active low logic input that is used in conjunction with to
enable the data outputs and with WR to allow input data to be written to the part.
28 22 RD Read Input. Active low logic input that is used in conjunction with CS low to
enable the data outputs.
27 21 WR Write Input. Active low logic input used in conjunction with CS to latch the mul-
tiplexer address and software control information. The rising edge of this input
also initiates an internal pulse. When using the software start facility, this pulse
delays the point at which the track/hold goes into hold and conversion is initiated.
This allows the multiplexer to settle and the acquisition time of the track/hold to
elapse when a channel address is changed. If the SWCON bit of the control regis-
ter is set to 1, when this pulse times out, the track/hold then goes into hold and
conversion is initiated. If the SWCON bit of the control register is set to 0, the
track/hold and conversion sequence are unaffected by WR operation.
Data I/O Lines
There are 12 data input/output lines on the AD7891. When the part is configured for parallel mode (MODE = 1), the output data
from the part is provided at these 12 pins during a read operation. For a write operation in parallel mode, these lines provide access
to the part’s control register.
Parallel Read Operation
During a parallel read operation, the 12 lines become the 12 data bits containing the conversion result from the AD7891. These
data bits are labelled Data Bit 0 (LSB) to Data Bit 11 (MSB). They are three-state, TTL compatible outputs. Output data coding
is twos complement when the data FORMAT bit of the control register is 1, and straight binary when the data FORMAT bit of
the control register is 0.
PLCC Pin No. MQFP Pin No. Mnemonic Description
13 to 18, 7 to 12, DB0 to DB11 Data Bit 0 (LSB) to Data Bit 11 (MSB). Three-state TTL compatible
21 to 26 15 to 20 outputs that are controlled by the CS and RD inputs.
Parallel Write Operation
During a parallel write operation, the following functions can be written to the control register via the 12 data input/output pins.
PLCC Pin No. MQFP Pin No. Mnemonic Description
23 17 A0 Address Input. The status of this input during a parallel write operation is
latched to the A0 bit of the control register (see Control Register section).
22 16 A1 Address Input. The status of this input during a parallel write operation is
latched to the A1 bit of the control register (see Control Register section).
21 15 A2 Address Input. The status of this input during a parallel write operation is
latched to the A2 bit of the control register (see Control Register section).
24 18 SWCON Software Conversion Start. The status of this input during a parallel write
operation is latched to the SWCONV bit of the control register (see Control
Register section).
25 19 SWSTBY Software Standby Control. The status of this input during a parallel write
operation is latched to the SWSTBY bit of the control register (see Control
Register section).
26 20 FORMAT Data Format Selection. The status of this input during a parallel write operation is
latched to the FORMAT bit of the control register (see Control Register section).
AD7891
–8–
REV. D
SERIAL INTERFACE MODE FUNCTIONS
When the part is configured for serial mode (MODE = 0), five of the 12 data input/output lines provide serial interface functions.
These functions are outlined below.
PLCC Pin No. MQFP Pin No. Mnemonic Description
18 12 SCLK Serial Clock Input. This is an externally applied serial clock that is used to
load serial data to the control register and to access data from the
output register.
15 9 TFS Transmit Frame Synchronization Pulse. Active low logic input with serial
data expected after the falling edge of this signal.
16 10 RFS Receive Frame Synchronization Pulse. This is an active low logic input
with RFS provided externally as a strobe or framing pulse to access serial data
from the output register. For applications that require that data be transmitted
and received at the same time, RFS and TFS should be connected together.
21 15 DATA OUT Serial Data Output. Sixteen bits of serial data are provided with the
data FORMAT bit and the three address bits of the control register
preceding the 12 bits of conversion data. Serial data is valid on the falling
edge of SCLK for 16 edges after RFS goes low. Output conversion data
coding is twos complement when the FORMAT bit of the control register is
1 and straight binary when the FORMAT bit of the control register is 0.
17 11 DATA IN Serial Data Input. Serial data to be loaded to the control register is provided
at this input. The first six bits of serial data are loaded to the control
register on the first six falling edges of SCLK after TFS goes low. Serial
data on subsequent SCLK edges is ignored while TFS remains low.
13, 14 7, 8 TEST Test Pin. When the device is configured for serial mode of operation,
two of the pins which had been data inputs become test inputs. To ensure
correct operation of the device, both TEST inputs should be tied to a
logic low potential.
CONTROL REGISTER
The control register for the AD7891 contains six bits of information as described below. These six bits can be written to the control
register either in a parallel mode write operation or via a serial mode write operation. The default (power-on) condition of all bits in
the control register is 0. Six serial clock pulses must be provided to the part in order to write data to the control register. If TFS
returns high before six serial clock cycles, no data transfer takes place to the control register and the write cycle has to be restarted to
write data to the control register. However, if the SWCONV bit of the register was previously set to a Logic 1 and TFS is brought
high before six serial clock cycles, another conversion is initiated.
A2 Address Input. This input is the most significant address input for multiplexer channel selection.
A1 Address Input. This is the second most significant address input for multiplexer channel selection.
A0 Address Input. Least significant address input for multiplexer channel selection. When the address is written to
the control register, an internal pulse is initiated to allow for the multiplexer settling time and track/hold acquisi-
tion time before the track/hold goes into hold and conversion is initiated. When the internal pulse times out, the
track/hold goes into hold and conversion is initiated. The selected channel is given by the formula
AAA24 12 01¥+ ¥+ +
SWCONV Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the CONVST input. Con-
tinuous conversion starts do not take place when there is a 1 in this location. The internal pulse and the conver-
sion process are initiated when a 1 is written to this bit. With a 1 in this bit, the hardware conversion start, i.e.,
the CONVST input, is disabled. Writing a 0 to this bit enables the hardware CONVST input.
SWSTBY Standby Mode Input. Writing a 1 to this bit places the device in its standby or power-down mode. Writing a 0 to
this bit places the device in its normal operating mode.
FORMAT Data Format. Writing a 0 to this bit sets the conversion data output format to straight (natural) binary. This
data format is generally used for unipolar input ranges. Writing a 1 to this bit sets the conversion data output
format to twos complement. This output data format is generally used for bipolar input ranges.
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD7891ASZ-1

Mfr. #:
Buy AD7891ASZ-1
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Bipolar Inpt SGL-Sup Parallel 8CH 12B
Lifecycle:
New from this manufacturer.
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