MAX1631EAI+ Datasheet MAX1632EAI+, MAX1634CAI+, MAX1631EAI+ | P13-P15

MAX1630–MAX1635

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 13

Figure 4. Main PWM Comparator Block Diagram

FB_

REF

CSH_

CSL_

SLOPE COMPENSATION

R1 R2

TO PWM

LOGIC

OUTPUT DRIVER

UNCOMPENSATED

HIGH-SPEED

LEVEL TRANSLATOR

AND BUFFER

I2 I3 V

BIAS

In PWM mode, the controller operates as a fixed-

frequency current-mode controller where the duty ratio

is set by the input/output voltage ratio. The current-

mode feedback system regulates the peak inductor

current value as a function of the output-voltage error

signal. In continuous-conduction mode, the average

inductor current is nearly the same as the peak current,

so the circuit acts as a switch-mode transconductance

amplifier. This pushes the second output LC filter pole,

normally found in a duty-factor-controlled (voltage-

mode) PWM, to a higher frequency. To preserve inner-

loop stability and eliminate regenerative inductor

current “staircasing,” a slope compensation ramp is

summed into the main PWM comparator to make the

apparent duty factor less than 50%.

The MAX1630 family uses a relatively low loop gain,

allowing the use of lower-cost output capacitors. The

relative gains of the voltage-sense and current-sense

inputs are weighted by the values of current sources

that bias three differential input stages in the main PWM

comparator (Figure 4). The relative gain of the voltage

comparator to the current comparator is internally fixed

at K = 2:1. The low loop gain results in the 2% typical

load-regulation error. The low value of loop gain helps

reduce output filter capacitor size and cost by shifting

the unity-gain crossover frequency to a lower level.

The output filter capacitors (Figure 1, C1 and C2) set a

dominant pole in the feedback loop that must roll off the

loop gain to unity before encountering the zero intro-

duced by the output capacitor’s parasitic resistance

(ESR) (see Design Procedure section). A 60kHz pole-

zero cancellation filter provides additional rolloff above

the unity-gain crossover. This internal 60kHz lowpass

compensation filter cancels the zero due to filter capaci-

tor ESR. The 60kHz filter is included in the loop in both

fixed-output and adjustable-output modes.

Synchronous Rectifier Driver (DL)

Synchronous rectification reduces conduction losses in

the rectifier by shunting the normal Schottky catch diode

with a low-resistance MOSFET switch. Also, the synchro-

nous rectifier ensures proper start-up of the boost gate-

driver circuit. If the synchronous power MOSFETs are

omitted for cost or other reasons, replace them with a

small-signal MOSFET, such as a 2N7002.

If the circuit is operating in continuous-conduction

mode, the DL drive waveform is simply the complement

of the DH high-side drive waveform (with controlled

dead time to prevent cross-conduction or “shoot-

through”). In discontinuous (light-load) mode, the syn-

chronous switch is turned off as the inductor current

falls through zero. The synchronous rectifier works

MAX1630–MAX1635

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

14 ______________________________________________________________________________________

under all operating conditions, including Idle Mode.

The SECFB signal further controls the synchronous

switch timing in order to improve multiple-output cross-

regulation (see Secondary Feedback Regulation Loop

section).

Internal VL and REF Supplies

An internal regulator produces the +5V supply (VL) that

powers the PWM controller, logic, reference, and other

blocks within the IC. This 5V low-dropout linear regula-

tor supplies up to 25mA for external loads, with a

reserve of 25mA for supplying gate-drive power.

Bypass VL to GND with 4.7µF.

Important: Ensure that VL does not exceed 6V.

Measure VL with the main output fully loaded. If it is

pumped above 5.5V, either excessive boost diode

capacitance or excessive ripple at V+ is the probable

cause. Use only small-signal diodes for the boost cir-

cuit (10mA to 100mA Schottky or 1N4148 are pre-

ferred), and bypass V+ to PGND with 4.7µF directly at

the package pins.

The 2.5V reference (REF) is accurate to ±2% over tem-

perature, making REF useful as a precision system ref-

erence. Bypass REF to GND with 1µF minimum. REF

can supply up to 5mA for external loads. (Bypass REF

with a minimum 1µF/mA reference load current.)

However, if extremely accurate specifications for both

the main output voltages and REF are essential, avoid

loading REF more than 100µA. Loading REF reduces

the main output voltage slightly, because of the refer-

ence load-regulation error.

When the 5V main output voltage is above 4.5V, an

internal P-channel MOSFET switch connects CSL5 to

VL, while simultaneously shutting down the VL linear

regulator. This action bootstraps the IC, powering the

internal circuitry from the output voltage, rather than

through a linear regulator from the battery.

Bootstrapping reduces power dissipation due to gate

charge and quiescent losses by providing that power

from a 90%-efficient switch-mode source, rather than

from a much less efficient linear regulator.

Boost High-Side Gate-Drive Supply

(BST3 and BST5)

Gate-drive voltage for the high-side N-channel switches

is generated by a flying-capacitor boost circuit

(Figure 2). The capacitor between BST_ and LX_ is

alternately charged from the VL supply and placed par-

allel to the high-side MOSFET’s gate-source terminals.

On start-up, the synchronous rectifier (low-side

MOSFET) forces LX_ to 0V and charges the boost

capacitors to 5V. On the second half-cycle, the SMPS

turns on the high-side MOSFET by closing an internal

switch between BST_ and DH_. This provides the nec-

essary enhancement voltage to turn on the high-side

switch, an action that “boosts” the 5V gate-drive signal

above the battery voltage.

Ringing at the high-side MOSFET gate (DH3 and DH5)

in discontinuous-conduction mode (light loads) is a nat-

ural operating condition. It is caused by residual ener-

gy in the tank circuit, formed by the inductor and stray

capacitance at the switching node, LX. The gate-drive

negative rail is referred to LX, so any ringing there is

directly coupled to the gate-drive output.

Current-Limiting and Current-Sense

Inputs (CSH and CSL)

The current-limit circuit resets the main PWM latch and

turns off the high-side MOSFET switch whenever the

voltage difference between CSH and CSL exceeds

100mV. This limiting is effective for both current flow

directions, putting the threshold limit at ±100mV. The

tolerance on the positive current limit is ±20%, so the

external low-value sense resistor (R1) must be sized for

80mV/I

PEAK

, where I

PEAK

is the required peak inductor

current to support the full load current, while compo-

nents must be designed to withstand continuous cur-

rent stresses of 120mV/R1.

For breadboarding or for very-high-current applications,

it may be useful to wire the current-sense inputs with a

twisted pair, rather than PC traces. (This twisted pair

needn’t be anything special; two pieces of wire-wrap

wire twisted together are sufficient.) This reduces the

possible noise picked up at CSH_ and CSL_, which can

cause unstable switching and reduced output current.

The CSL5 input also serves as the IC’s bootstrap sup-

ply input. Whenever V

CSL5

> 4.5V, an internal switch

connects CSL5 to VL.

Oscillator Frequency and

Synchronization (SYNC)

The SYNC input controls the oscillator frequency. Low

selects 200kHz; high selects 300kHz. SYNC can also

be used to synchronize with an external 5V CMOS or

TTL clock generator. SYNC has a guaranteed 240kHz

to 350kHz capture range. A high-to-low transition on

SYNC initiates a new cycle.

300kHz operation optimizes the application circuit for

component size and cost. 200kHz operation provides

increased efficiency, lower dropout, and improved

load-transient response at low input-output voltage dif-

ferences (see Low-Voltage Operation section).

MAX1630–MAX1635

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

______________________________________________________________________________________ 15

Table 4. Operating Modes

SEQ RUN/ON3 DESCRIPTION

XLow X All circuit blocks turned off. Supply current = 4µA.

SHDN

TIME/ON5

MODE

Shutdown

Low StandbyLowHigh Ref Both SMPSs off. Supply current = 30µA.

Low RunHigh

High RunLowHigh Ref 5V SMPS enabled/3.3V off

High Ref 3.3V SMPS enabled/5V off

High RunHigh

Timing capacitor StandbyLowHigh GND Both SMPSs off. Supply current = 30µA.

Timing capacitor RunHigh

Timing capacitor StandbyLowHigh VL Both SMPSs off. Supply current = 30µA.

High

High Ref Both SMPSs enabled

GND Both SMPSs enabled. 5V enabled before 3.3V.

Timing capacitor RunHighHigh VL Both SMPSs enabled. 3.3V enabled before 5V.

X = Don’t Care

Shutdown Mode

Holding SHDN low puts the IC into its 4µA shutdown

mode. SHDN is logic input with a threshold of about 1V

(the V

of an internal N-channel MOSFET). For auto-

matic start-up, bypass SHDN to GND with a 0.01µF

capacitor and connect it to V+ through a 220kΩ resistor.

Power-Up Sequencing

and ON/

OFF

Controls

Start-up is controlled by RUN/ON3 and TIME/ON5 in

conjunction with SEQ. With SEQ tied to REF, the two

control inputs act as separate ON/OFF controls for

each supply. With SEQ tied to VL or GND, RUN/ON3

becomes the master ON/OFF control input and

TIME/ON5 becomes a timing pin, with the delay

between the two supplies determined by an external

capacitor. The delay is approximately 800µs/nF. The

+3.3V supply powers-up first if SEQ is tied to VL, and

the +5V supply is first if SEQ is tied to GND. When driv-

ing TIME/ON5 as a control input with external logic,

always place a resistor (>1kΩ) in series with the input.

This prevents possible crowbar current due to the inter-

nal discharge pull-down transistor, which turns on in

standby mode and momentarily at the first power-up or

in shutdown mode.

RESET

Power-Good Voltage Monitor

The power-good monitor generates a system RESET sig-

nal. At first power-up, RESET is held low until both the

3.3V and 5V SMPS outputs are in regulation. At this point,

an internal timer begins counting oscillator pulses, and

RESET continues to be held low until 32,000 cycles have

elapsed. After this timeout period (107ms at 300kHz or

160ms at 200kHz), RESET is actively pulled up to VL. If

SEQ is tied to REF (for separate ON3/ON5 controls), only

the 3.3V SMPS is monitored—the 5V SMPS is ignored.

Output Undervoltage Shutdown Protection

(MAX1630/MAX1631/MAX1632)

The output undervoltage lockout circuit is similar to

foldback current limiting, but employs a timer rather

than a variable current limit. Each SMPS has an under-

voltage protection circuit that is activated 6144 clock

cycles after the SMPS is enabled. If either SMPS output

is under 70% of the nominal value, both SMPSs are

latched off and their outputs are clamped to ground by

the synchronous rectifier MOSFETs (see Output

Overvoltage Protection section). They won’t restart until

SHDN or RUN/ON3 is toggled, or until V+ power is

cycled below 1V. Note that undervoltage protection can

make prototype troubleshooting difficult, since you

have only 20ms or 30ms to figure out what might be

wrong with the circuit before both SMPSs are latched

off. In extreme cases, it may be useful to substitute the

MAX1633/MAX1634/MAX1635 into the prototype

breadboard until the prototype is working properly.

Output Overvoltage Protection

(MAX1630/MAX1631/MAX1632)

Both SMPS outputs are monitored for overvoltage. If

either output is more than 7% above the nominal regu-

lation point, both low-side gate drivers (DL_) are

latched high until SHDN or RUN/ON3 is toggled, or until

V+ power is cycled below 1V. This action turns on the

synchronous rectifiers with 100% duty, in turn rapidly

discharging the output capacitors and forcing both

SMPS outputs to ground. The DL outputs are also kept

high whenever the corresponding SMPS is disabled,

and in shutdown if VL is sustained.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

MAX1631EAI+

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Maxim Integrated

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Switching Controllers Multi-Out Low-Noise Power-Supply Ctlr

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MAX1631EAI+

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