.......................Document #: 38-07703 Rev. ** Page 16 of 18
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
t
P
Period Measured on rising edge at 1.5V 30 – – ns
t
H
High Time Duration of clock cycle above 2.4V 12 – – ns
t
L
Low Time Duration of clock cycle below 0.4V 12 – – ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 1 – 4 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 1 – 4 V/ns
t
D
Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 %
t
JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
––500ps
t
SK
Output Skew Measured on rising edge at 1.5V – – 500 ps
t
O
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1.5 – 4 ns
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
––3ms
Z
o
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
–30–
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
t
P
Period Measured on rising edge at 1.5V 15 – – ns
t
H
High Time Duration of clock cycle above 2.4V 5.25 – – ns
t
L
Low Time Duration of clock cycle below 0.4V 5.05 – – ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 1 – 4 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 1 – 4 V/ns
t
D
Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 %
t
JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
– – 500 ps
t
SK
Output Skew Measured on rising edge at 1.5V – – 250 ps
f
ST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
––3ms
Z
o
AC Output Impedance Average value during switching transition. Used
for determining series termination value.
–30–
APIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments Min. Typ. Max. Unit
f Frequency, Actual Frequency generated from PCI divided by 2 PCI/2 MHz
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns
t
F
Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns
t
D
Duty Cycle Measured on rising and falling edge at 1.5V 45 55 %
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Z
o
AC Output Impedance Average value during switching transition. Used
for determining series termination value.
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