W311
.........................Document #: 38-07703 Rev. ** Page 7 of 18
Byte 6: Reserved Register
Bit Name Default Pin Description
Bit 7 Reserved 1 Reserved
Bit 6 Reserved 1 Reserved
Bit 5 Reserved 1 Reserved
Bit 4 Reserved 1 Reserved
Bit 3 Reserved 1 Reserved
Bit 2 Reserved 1 Reserved
Bit 1 Reserved 1 Reserved
Bit 0 Reserved 1 Reserved
Byte 7: Reserved Register
Bit Name Default Pin Description
Bit 7 Reserved 1 Reserved
Bit 6 Reserved 1 Reserved
Bit 5 Reserved 1 Reserved
Bit 4 Reserved 1 Reserved
Bit 3 Reserved 1 Reserved
Bit 2 Reserved 1 Reserved
Bit 1 Reserved 1 Reserved
Bit 0 Reserved 1 Reserved
Byte 8: Vendor ID and Revision ID Register (Read Only)
Bit Name Default Pin Description
Bit 7 Revision_ID3 0 Revision ID bit[3]
Bit 6 Revision_ID2 0 Revision ID bit[2]
Bit 5 Revision_ID1 0 Revision ID bit[1]
Bit 4 Revision_ID0 0 Revision ID bit[0]
Bit 3 Vendor_ID3 1 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 2 Vendor_ID2 0 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 1 Vendor _ID1 0 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 0 Vendor _ID0 0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.
W311
.........................Document #: 38-07703 Rev. ** Page 8 of 18
Byte 9: System Reset and Watchdog Timer Register
Bit Name Default Pin Description
Bit 7 Reserved 0 Reserved
Bit 6 PCI_DRV 0 PCI clock output drive strength
0 = Normal
1 = High Drive
Bit 5 Reserved 0 Reserved
Bit 4 RST_EN_WD 0 This bit will enable the generation of a Reset pulse when a watchdog timer
time-out occurs.
0 = Disabled
1 = Enabled
Bit 3 RST_EN_FC 0 This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Bit 2 WD_TO_STATU
S
0 Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
Bit 1 WD_EN 0 0 = Stop and re-load Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down after a frequency
change occurs.
Note: W311 will generate system reset, reload a recovery frequency, and lock
itself into a recovery frequency mode after a watchdog timer time-out occurs.
Under recovery frequency mode, W311 will not respond to any attempt to
change output frequency via the SMBus control bytes. System software can
unlock W311 from its recovery frequency mode by clearing the WD_EN bit.
Bit 0 Reserved 0 Reserved
Byte 10: Skew Control Register
Bit Name Default Description
Bit 7 CPU_Skew2 0 CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 6 CPU_Skew1 0
Bit 5 CPU_Skew0 0
Bit 4 Reserved 0 Reserved
Bit 3 Reserved 0 Reserved
Bit 2 Reserved 0 Reserved
Bit 1 AGP_Skew1 0 AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Bit 0 AGP_Skew0 0
W311
.........................Document #: 38-07703 Rev. ** Page 9 of 18
Byte 11: Recovery Frequency N - Value Register
Bit Name Default Description
Bit 7 ROCV_FREQ_N7 0 If ROCV_FREQ_SEL is set, W311 will use the values programmed in ROCV_-
FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output
frequency.when a Watchdog Timer time-out occurs.
The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM,
AGP and SDRAM. When it is cleared, W311 will use the same frequency ratio
stated in the Latched FS[4:0] register. When it is set, W311 will use the
frequency ratio stated in the SEL[4:0] register.
W312 supports programmable CPU frequency ranging from 50 MHz to 248
MHz.
W311 will change the output frequency whenever there is an update to either
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended
to use Word or Block write to update both registers within the same SMBus bus
operation.
Bit 6 ROCV_FREQ_N6 0
Bit 5 ROCV_FREQ_N5 0
Bit 4 ROCV_FREQ_N4 0
Bit 3 ROCV_FREQ_N3 0
Bit 2 ROCV_FREQ_N2 0
Bit 1 ROCV_FREQ_N1 0
Bit 0 ROCV_FREQ_N0 0
Byte 12: Recovery Frequency M- Value Register
Bit Name Default Pin Description
Bit 7 ROCV_FREQ_SEL 0 ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog Timer time-out occurs. The clock generator will automatically
switch to the recovery CPU frequency based on the selection on ROCV_FRE-
Q_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]
Bit 6 ROCV_FREQ_M6 0 If ROCV_FREQ_SEL is set, W311 will use the values programmed in ROCV_-
FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU
output frequency.when a Watchdog Timer time-out occurs.The setting of
FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and
SDRAM. When it is cleared, W311 will use the same frequency ratio stated in
the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio
stated in the SEL[4:0] register. W311 supports programmable CPU frequency
ranging from 50 MHz to 248 MHz.
Bit 5 ROCV_FREQ_M5 0
Bit 4 ROCV_FREQ_M4 0
Bit 3 ROCV_FREQ_M3 0
Bit 2 ROCV_FREQ_M2 0
Bit 1 ROCV_FREQ_M1 0
Bit 0 ROCV_FREQ_M0 0
Byte 13: Programmable Frequency Select N-Value Register
Bit Name Default Pin Description
Bit 7 CPU_FSEL_N7 0 If Prog_Freq_EN is set, W311 will use the values programmed in CPU_F-
SEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency.
The new frequency will start to load whenever CPU_FSELM[6:0] is updated.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set, W311
will use the frequency ratio stated in the SEL[4:0] register. W311 supports
programmable CPU frequency ranging from 50 MHz to 248 MHz.
Bit 6 CPU_FSEL_N6 0
Bit 5 CPU_FSEL_N5 0
Bit 4 CPU_FSEL_N4 0
Bit 3 CPU_FSEL_N3 0
Bit 2 CPU_FSEL_N2 0
Bit 1 CPU_FSEL_N1 0
Bit 0 CPU_FSEL_N0 0

CYW311OXC

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products System Clock for VIATM Pro-266 DDR Chipset, W311 datasheet
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